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| Patent # | Description |
|---|---|
| 2017/0330870 |
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first... |
| 2017/0330869 |
Light-Emitting Module Provided is a light-emitting module that achieves high brightness, whose electrode structure is simple and whose brightness distribution has rotational... |
| 2017/0330868 |
LIGHT EMITTING DEVICE The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting... |
| 2017/0330867 |
TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS
OF MICRO-LED The present invention discloses a transferring method, a manufacturing method, a device and an electronic apparatus of micro-LED. The method for transferring... |
| 2017/0330866 |
PIXEL UNIT STRUCTURE AND MANUFACTURING METHOD THEREOF A pixel unit structure, as well as a manufacturing method thereof, is provided. The pixel unit structure includes a display medium module and an active... |
| 2017/0330865 |
SEMICONDUCTOR DEVICE The reliability of a semiconductor device is improved. A semiconductor device in accordance with one embodiment has a plurality of stacked semiconductor chips.... |
| 2017/0330864 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a... |
| 2017/0330863 |
3D INTEGRATION USING Al-Ge EUTECTIC BOND INTERCONNECT A method includes aligning a germanium feature on a first CMOS wafer with an aluminum feature on a second CMOS wafer. The aluminum feature and the germanium... |
| 2017/0330862 |
Semiconductor Device Having Stacked Semiconductor Chips Interconnected Via
TSV A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via... |
| 2017/0330861 |
NOVEL METHOD FOR ELECTROMAGNETIC SHIELDING AND THERMAL MANAGEMENT OF
ACTIVE COMPONENTS The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet... |
| 2017/0330860 |
DATA STORAGE DEVICE HAVING MULTI-STACK CHIP PACKAGE AND OPERATING METHOD
THEREOF Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip... |
| 2017/0330859 |
BARRIER LAYER FOR INTERCONNECTS IN 3D INTEGRATED DEVICE An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device... |
| 2017/0330858 |
Multi-Stack Package-on-Package Structures Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first... |
| 2017/0330857 |
TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS
OF MICRO-LED The present invention discloses a transferring method, a manufacturing method, a device and an electronic apparatus of micro-LED. The method for transferring... |
| 2017/0330856 |
ASSEMBLING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS
OF FLIP-DIE The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a... |
| 2017/0330855 |
System and Method for Immersion Bonding A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first... |
| 2017/0330854 |
BALL FORMING DEVICE FOR WIRE BONDER A ball forming device includes a first current control circuit to control discharge current arranged between a leading end of a wire and one electrode of a... |
| 2017/0330853 |
COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated... |
| 2017/0330852 |
MODULE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the... |
| 2017/0330851 |
DOUBLE PLATED CONDUCTIVE PILLAR PACKAGE SUBSTRATE The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the... |
| 2017/0330850 |
METHOD FOR MANUFACTURING ALLOY BUMP In order to manufacture an alloy bump, a resist pattern having openings which expose a substrate is formed on the substrate, an under-bump metal is formed on... |
| 2017/0330849 |
SMART BGA CHIP MAINTENANCE DEVICE The present invention relates to a smart BGA chip maintenance device comprising a base, a moving worktable, a horizontal slide, a vertical slide, a grinding... |
| 2017/0330848 |
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT Some embodiments relate to a bond pad structure of an integrated circuit (IC). In one embodiment the bond structure includes a bond pad and an intervening... |
| 2017/0330847 |
CAMERA MODULE, METHOD FOR MANUFACTURING CAMERA MODULE, IMAGING APPARATUS,
AND ELECTRONIC INSTRUMENT The present technology relates to a camera module capable of reducing the number of steps in the manufacturing process and reducing a black spot failure, a... |
| 2017/0330846 |
SWITCH CIRCUIT PACKAGE MODULE A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch... |
| 2017/0330845 |
VERSATILE AND RELIABLE INTELLIGENT PACKAGE A package comprises a body, and an electrically conductive pattern supported by said body. An interface portion is configured to receive a module to a... |
| 2017/0330844 |
TAMPER-PROOF ELECTRONIC PACKAGES WITH STRESSED GLASS COMPONENT
SUBSTRATE(S) Tamper-proof electronic packages and fabrication methods are provided which include a glass substrate. The glass substrate is stressed glass with a... |
| 2017/0330843 |
Advanced Moisture Resistant Structure of Compound Semiconductor Integrated
Circuits An advanced moisture resistant structure of compound semiconductor integrated circuit comprises a compound semiconductor substrate, a compound semiconductor... |
| 2017/0330842 |
Semiconductor Assembly and Method of Fabricating a Semiconductor Structure A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements... |
| 2017/0330841 |
Floating Die Package A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials... |
| 2017/0330840 |
Semiconductor Device and Method of Forming Electromagnetic (EM) Shielding
for LC Circuits A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is... |
| 2017/0330839 |
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present... |
| 2017/0330838 |
SEMICONDUCTOR PACKAGE A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers... |
| 2017/0330837 |
Contacting Embedded Electronic Component Via Wiring Structure in a
Component Carrier's Surface Portion With... A component carrier for carrying electronic components, wherein the component carrier comprises an at least partially electrically insulating core, at least... |
| 2017/0330836 |
CTE COMPENSATION FOR WAFER-LEVEL AND CHIP-SCALE PACKAGES AND ASSEMBLIES CTE compensation for wafer-level and chip-scale packages and assemblies. |
| 2017/0330835 |
EMBEDDED MULTI-DEVICE BRIDGE WITH THROUGH-BRIDGE CONDUCTIVE VIA SIGNAL
CONNECTION A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first... |
| 2017/0330834 |
CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a... |
| 2017/0330833 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time,... |
| 2017/0330832 |
AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the... |
| 2017/0330831 |
METALLIZATION OF THE WAFER EDGE FOR OPTIMIZED ELECTROPLATING PERFORMANCE
ON RESISTIVE SUBSTRATES A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an... |
| 2017/0330830 |
TRENCH SILICIDE WITH SELF-ALIGNED CONTACT VIAS A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a... |
| 2017/0330829 |
SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in... |
| 2017/0330828 |
MULTILAYER WIRING SUBSTRATE Provided is a multilayer wiring substrate capable of achieving excellent conduction reliability. The multilayer wiring substrate is formed by laminating an... |
| 2017/0330827 |
HYBRID EMBEDDED SURFACE MOUNT MODULE FORM FACTOR WITH SAME SIGNAL SOURCE
SUBSET MAPPING A surface mount module form factor comprises a substrate having a bottom surface, a top surface, and an outer periphery, with at least one electronic component... |
| 2017/0330825 |
LOW LOSS SUBSTRATE FOR HIGH DATA RATE APPLICATIONS In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first... |
| 2017/0330824 |
SIGNAL TRANSMISSION APPARATUS INCLUDING SEMICONDUCTOR CHIPS AND SIGNAL
ISOLATOR A signal transmission apparatus includes: a first lead frame; a second lead frame spaced from the first lead frame; a primary semiconductor chip electrically... |
| 2017/0330823 |
SYSTEMS AND METHODS FOR LEAD FRAME LOCKING DESIGN FEATURES Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package,... |
| 2017/0330822 |
LEADFRAME WITH VERTICALLY SPACED DIE ATTACH PADS A leadframe includes a first die attach pad ("DAP") having a first longitudinally extending edge surface and a second DAP having a first longitudinally... |
| 2017/0330821 |
3D-MICROSTRIP BRANCHLINE COUPLER The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture.... |
| 2017/0330820 |
METHOD FOR FABRICATION SEMICONDUCTOR DEVICE A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein... |
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