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| Patent # | Description |
|---|---|
| 2017/0357612 |
INFORMATION PROCESSING APPARATUS AND MAINTENANCE SYSTEM A disclosed information processing apparatus includes a memory and a processor coupled to the memory. And the processor is configured to detect that a first... |
| 2017/0357611 |
METHODS AND SYSTEMS TO ACHIEVE MULTI-TENANCY IN RDMA OVER CONVERGED
ETHERNET A method for providing multi-tenancy support for RDMA in a system that includes a plurality of physical hosts. Each each physical host hosts a set of data... |
| 2017/0357610 |
SPLIT NVME SSD IMPLEMENTATION USING NVME OVER FABRICS PROTOCOL One implementation of an NVMe storage system uses NVMe over Fabric (NVMf) SSDs. This implementation is built using off-the-shelf RDMA Network Interface Cards... |
| 2017/0357609 |
Multi-Port Interposer Architectures In Data Storage Systems Systems, methods, apparatuses, and architectures for storage interposers are provided herein. In one example, a storage interposer module includes Peripheral... |
| 2017/0357608 |
INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND
INFORMATION PROCESSING DEVICE This information processing system uses a simple configuration to control a remote device by employing a unified communication channel (pipe) from an... |
| 2017/0357607 |
BUILDING MANAGEMENT SYSTEM WITH AUTOMATIC EQUIPMENT DISCOVERY AND
EQUIPMENT MODEL DISTRIBUTION A building management system including a system manager, a zone coordinator, and one or more zone controllers configured to monitor and control building zones.... |
| 2017/0357606 |
CONFIGURATION VIA HIGH SPEED SERIAL LINK Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial... |
| 2017/0357605 |
System and Method for Independent, Direct and Parallel Communication Among
Multiple Field Programmable Gate Arrays Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe... |
| 2017/0357604 |
SYSTEM AND METHOD FOR OPERATING A DRR-COMPATIBLE ASYNCHRONOUS MEMORY
MODULE A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory... |
| 2017/0357603 |
SYSTEM AND METHOD FOR FILTERING FIELD PROGRAMMABLE GATE ARRAY INPUT/OUTPUT Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to... |
| 2017/0357602 |
METHODS AND SYSTEMS FOR FILTERING COMMUNICATION BETWEEN PERIPHERAL DEVICES
AND MOBILE COMPUTING DEVICES The embodiments are directed to methods and systems for sending and receiving signals between one or more peripheral devices connected to a dongle system and... |
| 2017/0357601 |
STORAGE MEDIUM STORING CACHE MISS ESTIMATION PROGRAM, CACHE MISS
ESTIMATION METHOD, AND INFORMATION PROCESSING... A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first... |
| 2017/0357600 |
MEMORY DEVICE, MEMORY MODULE, AND OPERATING METHOD OF MEMORY DEVICE A memory device, a memory module, and an operating method of the memory device are provided. The memory device includes a cell array storing a plurality of... |
| 2017/0357599 |
Enhancing Cache Performance by Utilizing Scrubbed State Indicators
Associated With Cache Entries Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may... |
| 2017/0357598 |
ADAPTIVE METHOD FOR SELECTING A CACHE LINE REPLACEMENT ALGORITHM IN A
DIRECT-MAPPED CACHE A method of managing a direct-mapped cache is provided. The method includes a direct-mapped cache receiving memory references indexed to a particular cache... |
| 2017/0357597 |
STORAGE CONTROLLER There is described a storage controller, the storage controller having an array of entries, each entry associated with a partition of one or more partitions,... |
| 2017/0357596 |
DYNAMICALLY ADJUSTABLE INCLUSION BIAS FOR INCLUSIVE CACHES A first cache that includes a plurality of cache lines and is inclusive of a second cache. The plurality of cache lines are associated with a plurality of... |
| 2017/0357595 |
TLB SHOOTDOWNS FOR LOW OVERHEAD Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising... |
| 2017/0357594 |
TRANSACTIONAL MEMORY THAT IS PROGRAMMABLE TO OUTPUT AN ALERT IF A
PREDETERMINED MEMORY WRITE OCCURS A transactional memory receives a command, where the command includes an address and a novel GAA (Generate Alert On Action) bit. If the GAA bit is set and if... |
| 2017/0357593 |
System and Method for Securing a Network Device A network device is provided. The network device includes a processor and a memory with code thereupon. The code when executed by the processor causes the... |
| 2017/0357592 |
ENHANCED-SECURITY PAGE SHARING IN A VIRTUALIZED COMPUTER SYSTEM An example method of page sharing in a host computer having virtualization software that supports execution of a plurality of virtualized computing instances... |
| 2017/0357591 |
CACHE MANAGEMENT IN A COMPOSITE DATA ENVIRONMENT Techniques and a system are provided for a cache manager system. The cache manager system includes features allowing the content selection system to determine... |
| 2017/0357590 |
Methods for Caching and Reading Data to be Programmed into a Storage Unit
and Apparatuses Using the Same The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the... |
| 2017/0357589 |
STORAGE SYSTEM AND METHOD FOR CONTROLLING CACHE When one of a plurality of storage apparatuses receives an input/output (IO) request in which the address of a logical volume is designated, a cache... |
| 2017/0357588 |
SCALED SET DUELING FOR CACHE REPLACEMENT POLICIES A processing system includes a cache that includes a cache lines that are partitioned into a first subset of the cache lines and a second subsets of the cache... |
| 2017/0357587 |
UP/DOWN PREFETCHER In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of... |
| 2017/0357586 |
SYNCHRONIZATION LOGIC FOR MEMORY REQUESTS In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory... |
| 2017/0357585 |
SETTING CACHE ENTRY AGE BASED ON HINTS FROM ANOTHER CACHE LEVEL A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to... |
| 2017/0357584 |
INSTRUCTION AND LOGIC FOR FLUSH-ON-FAIL OPERATION A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to... |
| 2017/0357583 |
ASYNCHRONOUS CACHE FLUSHING Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device... |
| 2017/0357582 |
AUTO ADDRESSING USING FUNCTIONAL CONNECTION An apparatus for auto addressing includes a communication bus interface configured to receive an address assignment request to assign an address to the... |
| 2017/0357581 |
MEMORY DEVICE CONTROLLING METHOD AND MEMORY DEVICE According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a... |
| 2017/0357580 |
Providing Multiple Memory Modes For A Processor Including Internal Memory In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package... |
| 2017/0357579 |
HYPERVISOR TRANSLATION BYPASS A system and method of translation bypass includes a hypervisor reserving a range of host virtual addresses. The hypervisor detects that a guest address is... |
| 2017/0357578 |
RECLAMATION OF IN-MEMORY DATABASE MEMORY RESOURCES A method for reclaiming memory resources may include segmenting a plurality of memory resources in an in-memory database into a first resource partition and a... |
| 2017/0357577 |
INTERVAL GARBAGE COLLECTION FOR MULTI-VERSION CONCURRENCY CONTROL IN
DATABASE SYSTEMS Technologies for performing garbage collection in database systems, such as multi-version concurrency control (MVCC) database systems, are described. For... |
| 2017/0357576 |
GROUP GARBAGE COLLECTION FOR MULTI-VERSION CONCURRENCY CONTROL IN DATABASE
SYSTEMS Technologies for performing garbage collection in database systems, such as multi-version concurrency control (MVCC) database systems, are described. For... |
| 2017/0357575 |
HYBRID GARBAGE COLLECTION FOR MULTI-VERSION CONCURRENCY CONTROL IN
DATABASE SYSTEMS Technologies for performing garbage collection in database systems, such as multi-version concurrency control (MVCC) database systems, are described. For... |
| 2017/0357574 |
HANDLING LARGE WRITES TO DISTRIBUTED LOGS A system includes writing of log data in chunks over a first range of heap log sequence positions of a heap log stored in the non-volatile memory system, and... |
| 2017/0357573 |
DATA STORAGE OPTIMIZATION FOR NON-VOLATILE MEMORY Non-volatile devices may be configured such that a clear operation on a single bit clears an entire block of bits. The representation of particular data... |
| 2017/0357572 |
MEMORY CONTROLLER, INFORMATION PROCESSING SYSTEM, AND MEMORY EXTENSION
AREA MANAGEMENT METHOD To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller... |
| 2017/0357571 |
MEMORY UNIT ASSIGNMENT AND SELECTION FOR INTERNAL MEMORY OPERATIONS IN
DATA STORAGE SYSTEMS Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The... |
| 2017/0357570 |
Storing Arrays of Data in Data Processing Systems In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit.times.N... |
| 2017/0357569 |
SYSTEM AND METHOD FOR AUTOMATIC ROOT CAUSE DETECTION A system, method, and computer-readable storage medium are provided to automatically detect a root cause for an error that occurred during execution of... |
| 2017/0357568 |
Device, Method, and Graphical User Interface for Debugging Accessibility
Information of an Application In accordance with some embodiments, a method is performed at a device with one or more processors, non-transitory memory, a display, and an input device. The... |
| 2017/0357567 |
APPLICATION LOGIC, AND VERIFICATION METHOD AND CONFIGURATION METHOD
THEREOF A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation... |
| 2017/0357566 |
MEMORY DEBUGGING TOOL FOR DISPLAYING OBJECTS WITHIN A NAVIGABLE GRAPH Described is a tool for allowing developers to analyze objects in to process virtual address space. The system includes a technique for identifying references... |
| 2017/0357565 |
COLLABORATIVE DATA SHARING AND DATA MODIFICATION APPLICATION Sharing data with various user devices may offer an opportunity for various software testing and troubleshooting procedures to optimally process software code... |
| 2017/0357564 |
MEASUREMENT COORDINATION BY MONITORING OF PROGRAM CODE EXECUTION The one or more processors of an electronic device execute program code. While executing the program code, measurements are performed on the electronic device... |
| 2017/0357563 |
Method, System for Automatic Monitoring, Control of Compliance of
Operations of Smart-City Infrastructure in... The present disclosure provides method and system for automatic monitoring and control of compliance of one or more operations of smart city infrastructure in... |
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