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Patent # Description
2018/0006015 CIRCUITRY WITH VOLTAGE LIMITING AND CAPACTIVE ENHANCEMENT
Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in...
2018/0006012 PROTECTION DEVICE AND OPERATION SYSTEM UTILIZING THE SAME
A protection device including a substrate, a first doped region, a first well region, a second doped region, a third doped region, a fourth doped region, a...
2018/0006010 INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a...
2018/0006009 INTEGRATED CIRCUIT LAYOUT AND METHOD OF CONFIGURING THE SAME
An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of...
2018/0006007 METHOD AND APPARATUS TO FACILITATE DIRECT SURFACE COOLING OF A CHIP WITHIN A 3D STACK OF CHIPS USING OPTICAL...
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having...
2018/0006006 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least...
2018/0006003 STRUCTURE AND METHOD FOR HYBRID OPTICAL PACKAGE WITH GLASS TOP COVER
An optical package containing optical sensor/detector pairs co-housed with a non-optical sensor and processes for fabricating the optical package are described...
2018/0006002 SEMICONDUCTOR CHIP PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor chip package includes a substrate; a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on...
2018/0006001 PACKAGED DEVICES WITH MULTIPLE PLANES OF EMBEDDED ELECTRONIC DEVICES
A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The...
2018/0005997 SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and...
2018/0005996 INPUT OUTPUT FOR AN INTEGRATED CIRCUIT
A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the...
2018/0005995 LAYOUT OF TRANSMISSION VIAS FOR MEMORY DEVICE
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory...
2018/0005991 INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A CHIP RECESS
IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be...
2018/0005988 Integrated DC-DC Power Converters Through Face-to-Face Bonding
DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In...
2018/0005984 Methods of Forming Multi-Die Package Structures Including Redistribution Layers
A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material...
2018/0005981 SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and...
2018/0005979 SIMULTANEOUS DOUBLE WIRE WEDGE BONDING METHOD, SYSTEM, KIT AND TOOL
A wedge bonding method for simultaneously connecting two wires to a first component and then to a second component includes a) feeding the two wires side by...
2018/0005978 METHOD FOR WAFER-WAFER BONDING
A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor...
2018/0005976 Mechanisms For Forming Bonding Structures
Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also...
2018/0005975 ENHANCED CLEANING FOR WATER-SOLUBLE FLUX SOLDERING
An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a...
2018/0005974 SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTED PACKAGE ON PACKAGE
A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication...
2018/0005973 STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES
A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the...
2018/0005971 BUMPED LAND GRID ARRAY
A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a...
2018/0005966 Integrated Tunable Filter Architecture
An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing...
2018/0005965 RLINK - ON-DIE INDUCTOR STRUCTURES TO IMPROVE SIGNALING
Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a...
2018/0005962 DAMAGING INTEGRATED CIRCUIT COMPONENTS
An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The...
2018/0005960 GLASS SUBSTRATE AND DISPLAY DEVICE COMPRISING THE SAME
Disclosed herein are methods for making a thin film device and/or for reducing warp in a thin film device, the methods comprising applying at least one metal...
2018/0005959 TRENCH MOSFET DEVICE AND THE PREPARATION METHOD THEREOF
A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a...
2018/0005958 METHODS FOR FORMING SHIELDED RADIO-FREQUENCY MODULES HAVING REDUCED AREA
Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing...
2018/0005956 Electronic Circuit and Substrate with Identification Pattern for Separate Electronic Circuits and Method for...
The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The...
2018/0005955 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The...
2018/0005950 ELECTRONIC COMPONENT DEVICE, METHOD OF MOUNTING ELECTRONIC COMPONENT DEVICE ON CIRCUIT BOARD, AND MOUNTING...
An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal...
2018/0005948 CHIP ON PRINTED CIRCUIT UNIT AND DISPLAY APPARATUS COMPRISING THE SAME
Disclosed is a printed circuit unit that includes a flexible member which has an upper surface and a lower surface and includes a first end and a second end....
2018/0005944 SUBSTRATE WITH SUB-INTERCONNECT LAYER
Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a...
2018/0005942 SEMICONDUCTOR DEVICE STRUCTURES
Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also...
2018/0005939 Techniques to Improve Reliability in Cu Interconnects Using Cu Intermetallics
Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a...
2018/0005938 MEMORY ARRAY STRUCTURE AND METHODS OF FABRICATING THEREOF
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The...
2018/0005937 ENHANCED SELF-ALIGNMENT OF VIAS FOR A SEMICONDUCTOR DEVICE
A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than...
2018/0005933 MANUFACTURING METHOD OF A CIRCUIT BOARD HAVING A GLASS FILM
Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A...
2018/0005932 VIA AND TRENCH FILLING USING INJECTION MOLDED SOLDERING
A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer...
2018/0005931 CIRCUIT REDISTRIBUTION STRUCTURE UNIT AND METHOD FOR MANUFACTURING CIRCUIT REDISTRIBUTION STRUCTURE
A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias...
2018/0005930 FAN-OUT PACKAGE STRUCTURE AND METHOD
A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure...
2018/0005929 FILM TYPE SEMICONDUCTOR PACKAGE
A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a...
2018/0005928 PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS
Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique...
2018/0005926 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an...
2018/0005925 PACKAGED SEMICONDUCTOR DEVICE HAVING A LEAD FRAME AND INNER AND OUTER LEADS AND METHOD FOR FORMING
A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner...
2018/0005923 SEMICONDUCTOR DEVICE
A semiconductor device includes: a circuit pattern, at least one or more wires joined thereto, an electrode terminal joining thereto, and a semiconductor...
2018/0005920 SEMICONDUCTOR DEVICE
In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion...
2018/0005919 SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon;...
2018/0005914 CIRCUIT BOARD AND ELECTRONIC DEVICE
A circuit board includes a metal circuit plate, a metallic heat diffusing plate disposed below the metal circuit plate and having an upper surface and a lower...
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