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Patent # Description
2018/0012847 SEMICONDUCTOR DEVICE
A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat...
2018/0012845 SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor...
2018/0012844 RUTHENIUM WIRING AND MANUFACTURING METHOD THEREOF
There is provided a ruthenium wiring, including: a TiON film formed as a base film in a recess formed in a predetermined film on a surface of a substrate; and...
2018/0012839 INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor...
2018/0012835 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device and a method for manufacturing the same are disclosed, which guarantee an overlay margin between a contact and a metal line. A method...
2018/0012834 COUPLING STRUCTURES FOR SIGNAL COMMUNICATION AND METHOD OF MAKING SAME
Techniques and mechanism to provide signal communication with vias variously extending in a substrate. In an embodiment, a first capacitor and a second...
2018/0012832 ELECTRODEPOSITED CONTACT TERMINAL FOR USE AS AN ELECTRICAL CONNECTOR OR SEMICONDUCTOR PACKAGING SUBSTRATE
An electrical connectors with electrodeposited terminals that are grown in place by electroplating cavities formed in a series of resist layers. The resist...
2018/0012831 SEMICONDUCTOR DEVICE
This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a...
2018/0012829 SEMICONDUCTOR PACKAGE WITH CLIP ALIGNMENT NOTCH
An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the...
2018/0012828 LEAD FRAME AND METHOD OF FABRICATING THE SAME
A lead frame is provided, including one or more power terminals and one or more control terminals, wherein at least one of the control terminals is externally...
2018/0012826 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and...
2018/0012823 SEMICONDUCTOR DEVICES, VIA STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a...
2018/0012820 HEAT SPREADERS WITH INTEGRATED PREFORMS
Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may...
2018/0012817 PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME
A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric...
2018/0012816 Circuit Package
A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.
2018/0012813 ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING
Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed...
2018/0012811 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base...
2018/0012808 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the...
2018/0012807 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first...
2018/0012806 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate...
2018/0012804 SEMICONDUCTOR DEVICE CHIP MANUFACTURING METHOD
Disclosed herein is a semiconductor device chip manufacturing method including a chipping prevention layer forming step of forming a chipping prevention layer...
2018/0012803 INTEGRATED DEVICE DIES AND METHODS FOR SINGULATING THE SAME
Integrated device dies and methods for forming one or more of the integrated device dies are disclosed. The integrated device dies can be formed using two step...
2018/0012802 ELEMENT CHIP MANUFACTURING METHOD
A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located...
2018/0012801 METHOD FOR PRODUCING A PLURALITY OF SEMICONDUCTOR CHIPS AND SEMICONDUCTOR CHIP
According to the present disclosure, a method for producing a plurality of semiconductor chips is provided with the following steps: a) providing a composite...
2018/0012800 DEVICE WITHOUT ZERO MARK LAYER
Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through...
2018/0012799 INTEGRATED ANTENNA ON INTERPOSER SUBSTRATE
Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground...
2018/0012797 METHOD FOR REDUCING VIA RC DELAY
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a...
2018/0012796 INTERCONNECT STRUCTURE FORMED WITH A HIGH ASPECT RATIO SINGLE DAMASCENE COPPER LINE ON A NON-DAMASCENE VIA
An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The...
2018/0012794 WIRING STRUCTURE AND METHOD OF FORMING A WIRING STRUCTURE
A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure...
2018/0012793 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric...
2018/0012792 SELECTIVE FILM DEPOSITION METHOD TO FORM AIR GAPS
A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor...
2018/0012791 INTERCONNECTS WITH INNER SACRIFICIAL SPACERS
Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is...
2018/0012789 ROBOTIC APPARATUS AND METHOD FOR TRANSPORT OF A WORKPIECE
A robotic apparatus for transporting a workpiece includes a first arm that pivots about a first axis and a second arm that is pivotably connected to the first...
2018/0012788 WAFER-FIXING TAPE, METHOD OF PROCESSING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR CHIP
A wafer-fixing tape, having: an temporary-adhesive layer provided on a substrate film, wherein the substrate film contains an ionomer resin comprising a...
2018/0012785 ELECTROSTATIC CHUCK WITH FEATURES FOR PREVENTING ELECTRICAL ARCING AND LIGHT-UP AND IMPROVING PROCESS UNIFORMITY
A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond...
2018/0012784 PLASMA PROCESSING-APPARATUS PROCESSING OBJECT SUPPORT PLATFORM, PLASMA PROCESSING APPARATUS, AND PLASMA...
According to one embodiment, a plasma processing-apparatus processing object support platform includes a lower plate, an upper plate, and a variable condenser....
2018/0012783 TRANSPORTING SYSTEM AND TRANSPORTING UNIT INCLUDED THEREIN
A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly...
2018/0012781 SUBSTRATE PROCESSING APPARATUS
A throughput in processing a substrate can be improved and a running cost thereof can be reduced. A substrate processing apparatus 1 that processes a substrate...
2018/0012777 SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD AND STORAGE MEDIUM
A substrate liquid processing apparatus includes a liquid processing unit configured to process a substrate by a processing liquid, and a controller. The...
2018/0012776 VACUUM ASSISTED SEALING PROCESSES & SYSTEMS FOR INCREASING AIR CAVITY PACKAGE MANUFACTURING RATES
The present disclosure describes a sealing processes and structure for sealing air cavity electronic packages using a thermosetting, thermal plastic, other...
2018/0012773 POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE
The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity...
2018/0012772 METHOD OF PLANARIZING SUBSTRATE SURFACE
A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material...
2018/0012771 METHOD OF PLANARIZING SUBSTRATE SURFACE
A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material...
2018/0012770 GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF...
A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN...
2018/0012769 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
2018/0012767 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base...
2018/0012766 METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR
A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a...
2018/0012762 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing...
2018/0012758 EPITAXIAL WAFER MANUFACTURING METHOD, EPITAXIAL WAFER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND...
A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes:...
2018/0012757 SEMICONDUCTOR STRUCTURE HAVING A GROUP III-V SEMICONDUCTOR LAYER COMPRISING A HEXAGONAL MESH CRYSTALLINE STRUCTURE
A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of Al.sub.XGa.sub.YIn.sub.(1-X-Y)N disposed on the substrate, stacks (107,...
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