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Patent # Description
2018/0047739 Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge...
An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a...
2018/0047738 SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE
A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk...
2018/0047737 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack...
2018/0047736 OTP CELL HAVING A REDUCED LAYOUT AREA
An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor...
2018/0047735 ONE TIME PROGRAMMABLE (OTP) CELL HAVING IMPROVED PROGRAMMING RELIABILITY
A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating...
2018/0047734 TRANSISTOR STRUCTURE HAVING N-TYPE AND P-TYPE ELONGATED REGIONS INTERSECTING UNDER COMMON GATE
A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated...
2018/0047733 Embedded SRAM and Methods of Forming the Same
A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor...
2018/0047732 MEMORY DEVICE HAVING VERTICAL STRUCTURE
A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating...
2018/0047731 Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
2018/0047730 SEMICONDUCTOR DEVICE
The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an...
2018/0047729 SiGe P-CHANNEL TRI-GATE TRANSISTOR BASED ON BULK SILICON AND FABRICATION METHOD THEREOF
A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three...
2018/0047728 METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an...
2018/0047727 PREVENTING SHORTING BETWEEN SOURCE AND/OR DRAIN CONTACTS AND GATE
Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source...
2018/0047726 INTEGRATED CIRCUIT HAVING OXIDIZED GATE CUT REGION AND METHOD TO FABRICATE SAME
A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon...
2018/0047725 SEMICONDUCTOR DEVICE
On a front surface side of an n.sup.- semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film...
2018/0047724 INTEGRATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
An integrated device includes a field effect transistor formed within and upon, an active region of a substrate and a resistor formed on an isolation region of...
2018/0047723 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film...
2018/0047722 SEMICONDUCTOR DEVICE
In a semiconductor device having an SJ structure, the reverse breakdown voltage decrease is suppressed while a main body region and a current detecting region...
2018/0047721 SEMICONDUCTOR DEVICE
To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device...
2018/0047720 CROSS-DOMAIN ESD PROTECTION
Semiconductor devices with cross-domain electrostatic discharge (ESD) protection and related fabrication methods are provided. An exemplary semiconductor...
2018/0047719 Method of Manufacturing a Semiconductor Die
A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the...
2018/0047718 SEMICONDUCTOR STRUCTURE OF ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing...
2018/0047717 ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the...
2018/0047716 Power Gating for Three Dimensional Integrated Circuits (3DIC)
Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure....
2018/0047715 STACK DEVICE HAVING VOLTAGE COMPENSATION
Stack device having voltage compensation. In some embodiments, a switching device can include switching elements connected in series between a first terminal...
2018/0047714 INTELLIGENT POWER MODULE AND MANUFACTURING METHOD THEREOF
An intelligent power module and a manufacturing method thereof are provided. The intelligent power module includes a radiator, an insulating layer, a circuit...
2018/0047713 METHOD OF FABRICATING AN OPTICAL MODULE THAT INCLUDES AN ELECTRONIC PACKAGE
Some forms include an electronic package that includes a photo-detecting receiver IC and a receiver IC. The electronic package includes a mold that encloses...
2018/0047712 LIGHT SOURCE MODULE, METHOD OF MANUFACTURING THE MODULE, AND BACKLIGHT UNIT INCLUDING THE LIGHT SOURCE MODULE
Provided are a light source module and a backlight unit (BLU) including the same. The light source module includes a substrate including a base plate extending...
2018/0047711 ELECTRONIC STACK STRUCTURE HAVING PASSIVE ELEMENTS AND METHOD FOR FABRICATING THE SAME
An electronic stack structure is provided, including a first substrate, a second substrate stacked on the first substrate through a plurality of passive...
2018/0047710 Method for Fabricating an Emissive Display using Laminated Printed Color Conversion Phosphor Sheets
Embodiments are related generally to electronic displays and, more particularly, to emissive displays made with transparent sheets having phosphor dots on the...
2018/0047709 Package-On-Package (PoP) Structure Including Stud Bulbs
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure...
2018/0047708 Semiconductor Packaging Structure and Method
A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A...
2018/0047707 3D SEMICONDUCTOR DEVICE AND STRUCTURE
An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors;...
2018/0047706 VERTICAL SEMICONDUCTOR DEVICE
A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device...
2018/0047705 INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS AND ELECTRICAL INTERCONNECTS FOR III-V...
Integrated circuits, methods for fabricating integrated circuits, and methods for fabricating electrical interconnects for III-V devices are provided. In an...
2018/0047704 MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIP
A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having...
2018/0047703 FORMATION METHOD OF CHIP PACKAGE
Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method...
2018/0047702 BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
2018/0047701 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first...
2018/0047700 Method for Remapping a Packaged Extracted Die with 3D Printed Bond Connections
A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the...
2018/0047699 BONDING APPARATUS AND BONDING SYSTEM
Deformation of substrates after the substrates are bonded can be suppressed. A bonding apparatus includes a first holding unit configured to attract and hold a...
2018/0047698 SEMICONDUCTOR DEVICE
An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor...
2018/0047696 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a...
2018/0047695 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material...
2018/0047694 SEMICONDUCTOR DEVICE
A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed...
2018/0047693 LPS SOLDER PASTE BASED LOW COST FINE PITCH POP INTERCONNECT SOLUTIONS
Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the...
2018/0047692 Method and System for Packing Optimization of Semiconductor Devices
Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging...
2018/0047691 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting...
2018/0047690 Elongated Bump Structures in Package Structure
A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured...
2018/0047689 ZN DOPED SOLDERS ON CU SURFACE FINISH FOR THIN FLI APPLICATION
Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device...
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