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Patent # Description
2018/0047688 Single-Shot Encapsulation
A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the...
2018/0047687 SEMICONDUCTOR ASSEMBLY AND METHOD OF MAKING SAME
A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package...
2018/0047686 METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE
A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width...
2018/0047685 Remapped Packaged Extracted Die
A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted...
2018/0047684 SEMICONDUCTOR DEVICE
A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a...
2018/0047683 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0047682 COMPOSITE BOND STRUCTURE IN STACKED SEMICONDUCTOR STRUCTURE
A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the...
2018/0047681 ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
Disclosed is an array substrate including: a metal pattern and an electrically conductive pattern formed sequentially on a base substrate, the electrically...
2018/0047680 SEMICONDUCTOR DEVICE
A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a BOX layer, an...
2018/0047679 DAMAGING INTEGRATED CIRCUIT COMPONENTS
An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The...
2018/0047678 TFT LIQUID CRYSTAL MODULES, PACKAGE STRUCTURES, AND PACKAGE METHODS
The present disclosure relates to a TFT liquid crystal module, and the package structure and the package method thereof. The TFT package structure includes a...
2018/0047677 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for...
2018/0047676 STRUCTURE AND FABRICATION METHOD FOR ENHANCED MECHANICAL STRENGTH CRACK STOP
Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After...
2018/0047675 CAVITY PACKAGE WITH COMPOSITE SUBSTRATE
An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower...
2018/0047674 METHOD OF MANUFACTURING REDISTRIBUTION CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING INTEGRATED FAN-OUT PACKAGE
A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An ...
2018/0047673 PACKAGE COMPRISING SWITCHES AND FILTERS
A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first...
2018/0047672 Interconnection Structure and Methods of Fabrication the Same
A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the...
2018/0047671 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2018/0047670 PROGRAMMABLE FUSE WITH SINGLE FUSE PAD AND CONTROL METHODS THEREOF
A fuse circuit that permits a fuse to be selected and programmed using a single fuse pad. The fuse circuit includes a fuse pad to receive a first voltage, a...
2018/0047669 III-V COMPATIBLE ANTI-FUSES
An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region...
2018/0047668 SEMICONDUCTOR RESISTOR STRUCTURES EMBEDDED IN A MIDDLE-OF-THE-LINE (MOL) DIELECTRIC
A resistor structure composed of a metal liner is embedded within a MOL dielectric material and is located, at least in part, on a surface of a doped...
2018/0047667 SEMICONDUCTOR DEVICE
A semiconductor device is provided with a SOI substrate including a semiconductor substrate, a BOX layer on the semiconductor substrate, and a semiconductor...
2018/0047666 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the...
2018/0047665 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a...
2018/0047664 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on...
2018/0047663 STANDALONE INTERFACE FOR STACKED SILICON INTERCONNECT (SSI) TECHNOLOGY INTEGRATION
Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect...
2018/0047662 INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive...
2018/0047661 WIRING BOARD
A wiring board includes an insulating layer including a first insulating film provided with a first surface and a second surface that is opposite to the first...
2018/0047660 LAND GRID ARRAY (LGA) PACKAGING OF PASSIVE-ON-GLASS (POG) STRUCTURE
A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a...
2018/0047659 SUPPORT TERMINAL INTEGRAL WITH DIE PAD IN SEMICONDUCTOR PACKAGE (AS AMENDED)
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first...
2018/0047658 SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY
A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the...
2018/0047657 ARRAY SUBSTRATE, CHIP ON FILM, DISPLAY PANEL AND DISPLAY DEVICE
Provided are an array substrate, a chip on film, a display panel and a display device. The array substrate has a display area and a bonding area located in a...
2018/0047656 HIGH POWER TRANSISTORS
High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than...
2018/0047655 THERMAL INTERFACE MATERIAL ON PACKAGE
A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes...
2018/0047654 TIM STRAIN MITIGATION IN ELECTRONIC MODULES
A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.
2018/0047653 WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE
The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with...
2018/0047652 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A POWER SEMICONDUCTOR DEVICE
A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on...
2018/0047651 MOLDING FOR LARGE PANEL FAN-OUT PACKAGE
The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises:...
2018/0047650 PACKAGING STRUCTURES WITH IMPROVED ADHESION AND STRENGTH
According to various aspects and embodiments, a support structure for packaging an electronic device is provided. In one example, a packaged electronic device...
2018/0047649 ELECTRONIC DEVICE
Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a...
2018/0047648 IC STRUCTURE INTEGRITY SENSOR HAVING INTERDIGITATED CONDUCTIVE ELEMENTS
A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including:...
2018/0047647 ANALYSIS METHOD FOR SILANOL GROUP OF SUBSTRATE SURFACE
A silanol group on a surface of a substrate having silicon on the surface thereof can be quantitatively analyzed with high accuracy. An analysis method for a...
2018/0047646 ACCURACY IMPROVEMENTS IN OPTICAL METROLOGY
Methods, metrology modules and target designs are provided, which improve the accuracy of metrology measurements. Methods provide flexible handling of multiple...
2018/0047645 SUPPRESSING INTERFACIAL REACTIONS BY VARYING THE WAFER TEMPERATURE THROUGHOUT DEPOSITION
Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a...
2018/0047644 METHOD AND STRUCTURE FOR FLIP-CHIP PACKAGE RELIABILITY MONITORING USING CAPACITIVE SENSORS GROUPS
Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time...
2018/0047643 Thermal Profile Monitoring Wafer And Methods Of Monitoring Temperature
Thermal monitors comprising a substrate with at least one camera position on a bottom surface thereof, a wireless communication controller and a battery. The...
2018/0047642 AIR GAP SPACER IMPLANT FOR NZG RELIABILITY FIX
A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation...
2018/0047641 TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS
A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region,...
2018/0047640 FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first...
2018/0047639 FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first...
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