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Patent # Description
2018/0061840 Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In...
A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The...
2018/0061839 SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE
A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a...
2018/0061838 MEMORY CELL
A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and...
2018/0061837 Memory Cells and Memory Arrays
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first...
2018/0061836 Memory Cells and Memory Arrays
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to...
2018/0061835 Memory Cells and Memory Arrays
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors....
2018/0061834 Memory Cells and Memory Arrays
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced...
2018/0061833 SUBSTRATE CONTACT LAND FOR AN MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE
A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS...
2018/0061832 METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a...
2018/0061831 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer....
2018/0061830 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate having a...
2018/0061829 VERTICAL FIELD EFFECT TRANSISTOR WITH UNIFORM GATE LENGTH
Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a...
2018/0061828 HIGH QUALITY DEEP TRENCH OXIDE
An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio...
2018/0061827 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MODULE
A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in...
2018/0061826 SEMICONDUCTOR DEVICE, LIQUID-DISCHARGE HEAD SUBSTRATE, LIQUID-DISCHARGE HEAD, AND LIQUID-DISCHARGE DEVICE
A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a...
2018/0061825 ELECTROSTATIC PROTECTION CIRCUIT, DISPLAY PANEL, AND DISPLAY APPARATUS
An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control...
2018/0061824 ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND FABRICATING METHOD THEREOF
An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a...
2018/0061823 Semiconductor Device Having an Electrostatic Discharge Protection Structure
A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A first isolation layer is...
2018/0061822 SEMICONDUCTOR INTEGRATED CIRCUIT
According to one embodiment, a semiconductor integrated circuit includes: a protection circuit including a first diode whose cathode is connected to a first...
2018/0061821 SEMICONDUCTOR DEVICE
The present disclosure provides a semiconductor device that may improve the discharge capacity with respect to ESD without increasing the surface area of the...
2018/0061820 MULTI-DIE INTEGRATED CIRCUIT DEVICE WITH OVERVOLTAGE PROTECTION
An apparatus includes a package, a plurality of external connections extending outside the package, and a first die having a first electrical contact coupled...
2018/0061819 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer...
2018/0061818 Semiconductor Device and Method of Manufacturing
A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is...
2018/0061817 SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME
Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips...
2018/0061816 SEMICONDUCTOR PACKAGES
A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first...
2018/0061815 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The...
2018/0061814 BACKLIGHT SYSTEM AND METHOD FOR MANUFACTURING THEREOF
A backlight system includes a backlight module. The backlight module includes a light source array with a plurality of micro LEDs. The backlight module defines...
2018/0061813 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on...
2018/0061812 METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES
Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor...
2018/0061811 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill....
2018/0061810 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked...
2018/0061809 ELECTRONIC PACKAGE STRUCTURE WITH MULTIPLE ELECTRONIC COMPONENTS
An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of...
2018/0061808 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first...
2018/0061807 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes a first substrate, a second substrate, a sealing member, a first conductive member, and a second conductive member. Electronic...
2018/0061806 Semiconductor Device and Method of Forming SIP with Electrical Component Terminals Extending Out from Encapsulant
A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical...
2018/0061805 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The...
2018/0061804 METAL BONDING PADS FOR PACKAGING APPLICATIONS
Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured...
2018/0061803 BONDING DEVICE
[Problem] To provide a bonding device capable of adequately controlling a leading end of a capillary when a ball formed at a leading end of a wire is pressed...
2018/0061802 POWER SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE AND LOAD CURRENT TERMINAL ELEMENTS
The invention relates to a power semiconductor device with a substrate with a cooling device and power semiconductor components connected thereon, having load...
2018/0061801 FAN-OUT SEMICONDUCTOR PACKAGE MODULE
A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a ...
2018/0061800 REDUCTION OF SOLDER INTERCONNECT STRESS
An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major...
2018/0061799 REDUCTION OF SOLDER INTERCONNECT STRESS
A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis....
2018/0061798 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint...
2018/0061797 METHOD OF FORMING A SOLDER BUMP STRUCTURE
A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate,...
2018/0061796 METHOD OF FORMING A SOLDER BUMP STRUCTURE
A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate,...
2018/0061795 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0061794 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0061793 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality...
2018/0061792 UBM (UNDER BUMP METAL) ELECTRODE STRUCTURE FOR RADIATION DETECTOR, RADIATION DETECTOR AND PRODUCTION METHOD THEREOF
An UBM electrode structure body for a radiation detector and a radiation detector arranged with the UBM electrode structure body are provided for suppressing...
2018/0061791 SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS
Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least...
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