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Patent # Description
2018/0061739 DISTRIBUTION AND STABILIZATION OF FLUID FLOW FOR INTERLAYER CHIP COOLING
A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic...
2018/0061738 DISTRIBUTION AND STABILIZATION OF FLUID FLOW FOR INTERLAYER CHIP COOLING
A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic...
2018/0061737 HEAT SINK COOLING WITH PREFERRED SYNTHETIC JET COOLING DEVICES
An assembly of synthetic jet devices is provided for cooling a heat sink. The assembly includes a mounting member for coupling to a heat sink including a...
2018/0061736 HEAT DISSIPATING SHEET, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
The disclosed method of manufacturing an electronic device includes: placing a resin film on a component; and while heating the resin film to be softened,...
2018/0061735 SEMICONDUCTOR DEVICE
Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene...
2018/0061734 HEAT DISSIPATION STRUCTURE USING GRAPHENE QUANTUM DOTS AND METHOD OF MANUFACTURING THE HEAT DISSIPATION STRUCTURE
Disclosed are heat dissipation structures using nano-sized graphene fragments such as graphene quantum dots (GQDs) and/or methods of manufacturing the heat...
2018/0061733 CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER
An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat...
2018/0061732 CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER
An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat...
2018/0061731 ELECTRONIC CHIP DEVICE WITH IMPROVED THERMAL RESISTANCE AND ASSOCIATED MANUFACTURING PROCESS
An electronic chip device with improved thermal resistance comprises at least one electrical connection pad with an electrical interconnection link, at least...
2018/0061730 AIR CAVITY PACKAGE
The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body,...
2018/0061729 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first electronic component disposed on a first surface of a substrate, a first conductive member disposed on the first...
2018/0061728 DISPLAY PANEL WITH DAM STRUCTURE
A display panel includes a first inorganic capping layer (INOCL) in a non-displaying area (A.sub.ND) of a substrate, a first electrode in the A.sub.ND formed...
2018/0061727 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive...
2018/0061726 AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component,...
2018/0061725 AIR-CAVITY PACKAGE WITH ENHANCED PACKAGE INTEGRATION LEVEL AND THERMAL PERFORMANCE
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a...
2018/0061724 Method for Remapping a Packaged Extracted Die
A method for remapping an extracted die is provided. The method includes one or more of removing an extracted die from a previous integrated circuit package,...
2018/0061723 SCAN TESTABLE THROUGH SILICON VIAs
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
2018/0061722 DISPLAY DEVICE AND TESTING METHOD THEREOF
A display device and a testing method thereof are disclosed, in which a defect caused by an overflow of an organic film constituting an encapsulation film can...
2018/0061721 SELF-HEALING SEMICONDUCTOR WAFER PROCESSING
Implementations of the present disclosure generally relate to methods for processing substrates, and more particularly, to methods for predicting, quantifying...
2018/0061720 Techniques For Layer Fencing To Improve Edge Linearity
An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink...
2018/0061719 Fabrication Of Thin-Film Encapsulation Layer For Light Emitting Device
An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink...
2018/0061718 METHOD OF INSPECTING SURFACE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided are a method of inspecting a surface and a method of manufacturing a semiconductor device. The methods include preparing a substrate, selecting a...
2018/0061717 Flowable CVD Quality Control in STI Loop
A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a...
2018/0061716 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an isolation...
2018/0061715 Method of Forming Source/Drain Contact
Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is...
2018/0061714 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a substrate including a plurality...
2018/0061713 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE
A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction...
2018/0061712 METHOD OF TRANSFERRING A SEMICONDUCTOR LAYER
The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by...
2018/0061711 PROCESSING METHOD OF PACKAGE WAFER
A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral...
2018/0061710 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method includes forming a first mask over a semiconductor substrate including a first and second surfaces and an electrode...
2018/0061709 MARKED PIXEL UNIT, DISPLAY DEVICE USING THE SAME, AND METHOD FOR FABRICATING THE DISPLAY DEVICE
A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel...
2018/0061708 SELF-FORMING BARRIER FOR USE IN AIR GAP FORMATION
An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a...
2018/0061707 SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE
A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive...
2018/0061706 SEMICONDUCTOR DEVICE HAVING A Pd-CONTAINING ADHESION LAYER
According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing...
2018/0061705 NEUTRAL ATOM BEAM NITRIDATION FOR COPPER INTERCONNECT
A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening...
2018/0061704 NEUTRAL ATOM BEAM NITRIDATION FOR COPPER INTERCONNECT
A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening...
2018/0061703 COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS
An integrated circuit device has a substrate including a dielectric layer patterned with a pattern which includes a set of features in the dielectric for a set...
2018/0061701 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a...
2018/0061700 MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING ETCH PROCESSING TO OBTAIN DESIRED FEATURES
Embodiments are disclosed for processing microelectronic workpieces having patterned structures that include ultra-low dielectric constant (k) (ULK) material...
2018/0061699 MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS
A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask...
2018/0061698 Semiconductor Structure and Related Method
A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a...
2018/0061697 SEMICONDUCTOR DEVICE HAVING MIM CAPACITOR
A semiconductor device that provides a pad electrically connected to the metal layer and a capacitor connected to the pad is disclosed. The semiconductor...
2018/0061696 EDGE RING OR PROCESS KIT FOR SEMICONDUCTOR PROCESS MODULE
The present invention generally relates method and apparatus for detecting erosion to a ring assembly used in an etching or other plasma processing chamber. In...
2018/0061695 METHOD FOR PROCESSING A WAFER AND METHOD FOR PROCESSING A CARRIER
According to various embodiments, a method for processing a wafer may include scanning a focused laser beam over the wafer to form a defect structure within...
2018/0061694 ELECTRONIC POWER DEVICES INTEGRATED WITH AN ENGINEERED SUBSTRATE
A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier...
2018/0061693 TRANSPORT CONTAINER AND TRANSFER METHOD FOR STORED OBJECT
A transport container, in which a stored object is taken in and out through an opening on a side surface, includes a positioner that projects upward from an...
2018/0061692 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM
A substrate processing method is provided. The substrate processing method includes placing a substrate storage container storing a substrate on a load port;...
2018/0061691 Spectral Reflectometry For In-Situ Process Monitoring And Control
Methods and systems for performing in-situ, selective spectral reflectometry (SSR) measurements of semiconductor structures disposed on a wafer are presented...
2018/0061690 Substrate Processing Apparatus, Substrate Processing Method, and Recording Medium
A substrate processing apparatus includes a nozzle for discharging a processing solution, a processing solution supply part for supplying the processing...
2018/0061689 IN LINE FAN OUT SYSTEM
A system for fan out chip encapsulation processing is provided, wherein a plurality of microchips are encapsulated in molding compound, the system comprising:...
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