Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| 2018/0108604 |
CHIP ON FILM AND DISPLAY DEVICE Disclosed are a chip on film and a display device. the chip on film includes a plurality of output pads independent from each other extending in the first... |
| 2018/0108603 |
SEMICONDUCTOR DEVICE AND WIRING BOARD DESIGN METHOD The present disclosure provides a semiconductor device including: a semiconductor chip; a substrate including a first region where the semiconductor chip is... |
| 2018/0108602 |
FAN-OUT BALL GRID ARRAY PACKAGE STRUCTURE AND PROCESS FOR MANUFACTURING
THE SAME A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface... |
| 2018/0108601 |
MOLDED INTELLIGENT POWER MODULE AND METHOD OF MAKING THE SAME An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor... |
| 2018/0108600 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device of the present invention includes: a plurality of wiring boards disposed separately from one another; a plurality of semiconductor... |
| 2018/0108599 |
DIE PAD, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR
DEVICE The specification discloses a technique for preventing a bonding material from reaching the upper and lower surfaces of a semiconductor chip in bonding the... |
| 2018/0108598 |
MOLDED INTELLIGENT POWER MODULE An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor... |
| 2018/0108597 |
WIRE BONDING STRUCTURE AND ELECTRONIC DEVICE A wire bonding structure includes a bonding target and a wire with its bond portion bonded to the bonding target. The bond portion has a bottom surface in... |
| 2018/0108596 |
AIR GAP AND AIR SPACER PINCH OFF Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a... |
| 2018/0108595 |
DUAL MODULE FOR DUAL CHIP CARD A dual module for a dual chip card includes a supporting film supporting on an outer surface, a plurality of connecting pads including two series of connecting... |
| 2018/0108594 |
CARBON NANOTUBE STRUCTURE, HEAT DISSIPATION SHEET, AND METHOD OF
MANUFACTURING CARBON NANOTUBE STRUCTURE A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat... |
| 2018/0108593 |
BONDED BODY, SUBSTRATE FOR POWER MODULE WITH HEAT SINK, HEAT SINK, METHOD
FOR PRODUCING BONDED BODY, METHOD FOR... A bonded body is provided that is formed by bonding a metal member formed from copper, nickel, or silver, and an aluminum alloy member formed from an aluminum... |
| 2018/0108591 |
SEMICONDUCTOR DEVICE A semiconductor device includes a semiconductor module and a cooler. The semiconductor device includes semiconductor element(s) within a molded resin and a... |
| 2018/0108590 |
Conductive Line System and Process A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each... |
| 2018/0108589 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the... |
| 2018/0108588 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the... |
| 2018/0108587 |
METHOD FOR PASSIVATING A SURFACE OF A SEMICONDUCTOR AND RELATED SYSTEMS A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a... |
| 2018/0108586 |
LEAD BONDING STRUCTURE A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The... |
| 2018/0108585 |
CHIP PACKAGING STRUCTURE AND PACKAGING METHOD A chip package and packaging method are provided. The package includes: a substrate; a sensing chip coupled with the substrate, where the sensing chip has a... |
| 2018/0108584 |
Semiconductor Substrate A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a... |
| 2018/0108583 |
DEVICE CHIP, ACCOMMODATING TRAY, AND METHOD OF ACCOMMODATING DEVICE CHIPS A device chip is shaped as an inverted frustum with a device formed on an upper surface thereof. An accommodating tray for accommodating a plurality of device... |
| 2018/0108582 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected... |
| 2018/0108581 |
LID, AND OPTICAL DEVICE PACKAGE A lid constitutes, together with a housing, a package that encloses an optical element. The lid includes a frame plate divided into a first member and a second... |
| 2018/0108580 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR PRODUCT WAFER Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the... |
| 2018/0108579 |
SOLAR CELL EMITTER CHARACTERIZATION USING NON-CONTACT DOPANT CONCENTRATION
AND MINORITY CARRIER LIFETIME... A method and apparatus for estimating an effect of variations of wafer properties on operating parameters of photovoltaic cells during manufacturing is... |
| 2018/0108578 |
Metrology Systems And Methods For Process Control Methods and systems for estimating values of parameters of interest based on repeated measurements of a wafer during a process interval are presented herein.... |
| 2018/0108577 |
IC UNIT AND METHOND OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE
INCLUDING THE SAME There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an... |
| 2018/0108576 |
SEMICONDUCTOR ARRANGEMENT AND METHOD OF FORMING A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the... |
| 2018/0108575 |
FINFET DEVICE AND FABRICATION METHOD THEREOF A method for fabricating a Fin-FET device includes forming fin structures on a substrate and an isolation structure to cover a portion of sidewall surfaces of... |
| 2018/0108574 |
FINFET DEVICE AND FABRICATION METHOD THEREOF A FinFET device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the... |
| 2018/0108573 |
FIN-FET DEVICES AND FABRICATION METHODS THEREOF A method for fabricating a Fin-FET device includes providing a base structure and a plurality of fin structures protruding from the base structure. Along a... |
| 2018/0108572 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The... |
| 2018/0108571 |
METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL
LINE JUMPING OVER MOL FEATURES IN A... At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature.... |
| 2018/0108570 |
METHOD FOR MANUFACTURING FINS A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is... |
| 2018/0108569 |
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more... |
| 2018/0108568 |
LASER LIFT-OFF METHOD OF WAFER The present invention relates to a laser lift-off method of wafer. The method includes the steps as follows: focusing laser in an inside for a wafer (10) to... |
| 2018/0108567 |
SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor... |
| 2018/0108566 |
INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND
THROUGH-SILICON VIA AND METHOD OF FORMING SAME One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side... |
| 2018/0108565 |
METHOD OF LASER-PROCESSING DEVICE WAFER There is provided a method of laser-processing a device wafer with a laser beam applied thereto. The device wafer has a face side having thereon a plurality of... |
| 2018/0108564 |
DESIGN AND INTEGRATION OF FINFET DEVICE An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights... |
| 2018/0108563 |
METHOD OF FABRICATING ISOLATION STRUCTURE A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A... |
| 2018/0108562 |
PROTECTIVE COVER FOR ELECTROSTATIC CHUCK In embodiments, manufacturing a protective cover for an electrostatic chuck comprises coating a top surface and side walls of a conductive wafer with a plasma... |
| 2018/0108561 |
Robot Having Arm with Unequal Link Lengths An apparatus including at least one drive; a first robot arm having a first upper arm, a first forearm and a first end effector. The first upper arm is... |
| 2018/0108560 |
SUBSTRATE HOLDER Substrate holders having support plates for mounting of substrates are disclosed. The substrate holders use a combination of spring clamping elements and pins... |
| 2018/0108559 |
Methods and Systems for Chucking a Warped Wafer Methods and systems for vacuum mounting a warped, thin substrate onto a flat chuck are presented herein. A vacuum chuck includes three or more collapsible... |
| 2018/0108558 |
WAFER DE-BONDING DEVICE A wafer de-bonding device comprises a stage (1) for holding a device wafer and a carrier wafer bonded together, and a tool (2) with a gas outlet (2.2) disposed... |
| 2018/0108557 |
DEVICE COMPRISING FILM FOR ELECTROSTATIC COUPLING OF A SUBSTRATE TO A
SUBSTRATE CARRIER The invention relates to an apparatus for electrostatic coupling of a substrate with a substrate carrier, wherein the apparatus includes a flexible plastic... |
| 2018/0108556 |
MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR PRODUCING
THE SAME A method for producing a member for a semiconductor manufacturing apparatus 10 includes (a) a step of providing an electrostatic chuck 20, a supporting... |
| 2018/0108555 |
ELECTROSTATIC CHUCK DEVICE An electrostatic chuck device includes: a placing plate having a placement surface on which a plate-like sample is placed on one side thereof; an electrostatic... |
| 2018/0108554 |
METHOD FOR SELF-ALIGNING A THIN-FILM DEVICE ON A HOST SUBSTRATE A method for self-aligning a thin-film device on a host substrate is provided. A predetermined location on a host substrate is treated with a hydrophobic... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.