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Patent # Description
2018/0145191 Backside-Illuminated Photodetector Structure and Method of Making the Same
A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor...
2018/0145190 BROADBAND MULTI-PURPOSE OPTICAL DEVICE AND METHODS OF MANUFACTURING AND OPERATING THE SAME
A broadband multi-purpose optical device includes a semiconductor layer having a light absorption characteristic, a first active layer having a light...
2018/0145189 COATED GLASS FOR SOLAR REFLECTORS
The present invention relates to a heat treated coated glass for a solar reflector comprising: a heat treated glass, and an anti-soiling coating of TiO.sub.2...
2018/0145188 STACKED SEMICONDUCTOR STRUCTURE
A stacked semiconductor structure having a number of semiconductor diodes connected to one another in series, wherein each semiconductor diode has a p-n...
2018/0145187 LIQUID SEMICONDUCTOR-HALOGEN BASED ELECTRONICS
According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first...
2018/0145186 Packaged Overvoltage Protection Circuit For Triggering Thyristors
In a first embodiment, an ultra-fast breakover diode has a turn on time T.sub.ON that is less than 0.3 microseconds, where the forward breakover voltage is...
2018/0145185 TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME
An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and...
2018/0145184 NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT
A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a...
2018/0145183 VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate...
2018/0145182 A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the...
2018/0145181 BOTTOM GATE TYPE THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS
Provided is a bottom gate type thin film transistor including on a substrate (1) a gate electrode (2), a first insulating film (3) as a gate insulating film,...
2018/0145180 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the...
2018/0145179 DIALKYLZINC PARTIAL HYDROLYSATE-CONTAINING SOLUTION AND METHOD OF PRODUCTION OF ZINC OXIDE THIN FILM USING THE...
A dialkylzinc partial hydrolysate-containing solution which can be handled in air and can form a zinc oxide thin film in air and a method for producing the...
2018/0145178 STRAINED FINFET SOURCE DRAIN ISOLATION
A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a spacer...
2018/0145177 FinFET Structures and Methods of Forming the Same
FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate...
2018/0145176 MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF
A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a...
2018/0145175 Source/Drain Structure and Manufacturing the Same
A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of...
2018/0145174 TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN
Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques...
2018/0145173 EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION
In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain...
2018/0145172 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method...
2018/0145171 Field Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and Drain Contacts
An integrated circuit (IC) structure may include one or more trench-based semiconductor devices, e.g., field-effect transistors (trench FETs), having a...
2018/0145170 Method of Forming a Field-Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and...
A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain...
2018/0145169 METHOD FOR FABRICATING FINFET ISOLATION STRUCTURE
A method for forming a semiconductor device is provided. In this method, a stop layer is formed on a semiconductor substrate. A semiconductor fin is formed on...
2018/0145168 SILICON-CARBIDE TRENCH GATE MOSFETS AND METHODS OF MANUFACTURE
In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the...
2018/0145167 PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches...
2018/0145166 SEMICONDUCTOR DEVICE
A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 .mu.m-thick...
2018/0145165 LOW RESISTANCE AND LEAKAGE DEVICE
A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the...
2018/0145164 HETEROEPITAXIAL STRUCTURES WITH HIGH TEMPERATURE STABLE SUBSTRATE INTERFACE MATERIAL
Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline...
2018/0145163 Semiconductor Device having High Linearity-Transconductance
A semiconductor device includes a semiconductor structure including a first doped layer for forming a carrier channel having a carrier charge, a second doped...
2018/0145162 IGBT Die Structure With Auxiliary P Well Terminal
An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well...
2018/0145161 Semiconductor Device with Separation Regions
According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in...
2018/0145160 HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER
The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on...
2018/0145159 HETEROJUNCTION BIPOLAR TRANSISTOR
A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two...
2018/0145158 SEMICONDUCTOR DEVICE
A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface....
2018/0145157 PLASMA TREATMENT ON METAL-OXIDE TFT
Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the...
2018/0145156 FINFET WITH IMPROVED GATE DIELECTRIC
A semiconductor device includes a substrate structure comprising a substrate and a plurality of fins on the substrate. Each of the fins includes a...
2018/0145155 III-V FIN Generation By Lateral Growth On Silicon Sidewall
A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a...
2018/0145154 III-V FIN Generation By Lateral Growth On Silicon Sidewall
A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a...
2018/0145153 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor...
2018/0145152 DOPED POLY-SILICON FOR POLYCMP PLANARITY IMPROVEMENT
A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the...
2018/0145151 Metal Gate Scheme for Device and Methods of Forming
Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate,...
2018/0145149 SEMICONDUCTOR DEVICE GATE STRUCTURE AND METHOD OF FABRICATING THEREOF
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer...
2018/0145148 COMPOUND SEMICONDUCTOR DEVICE
A compound semiconductor device includes: a substrate; a channel layer formed over the substrate; a spacer structure formed over the channel layer; a barrier...
2018/0145147 METHOD FOR FABRICATING HIGH-VOLTAGE INSULATED GATE TYPE BIPOLAR SEMICONDUCTOR DEVICE
A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining...
2018/0145146 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE
The present disclosure provides a thin film transistor, a method for manufacturing the same, an array substrate and a display device. The method for...
2018/0145145 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE USING DOUBLE PATTERNING
A method for forming a semiconductor device structure is provided. The method includes forming a mandrel masking structure over a target layer. The method also...
2018/0145144 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a...
2018/0145143 Fin Field Effect Transistors having Conformal Oxide Layers and Methods of Forming Same
An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of...
2018/0145142 METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE WITH HIGH PRECISION OF FLOATING GATE FORMING
A method for fabricating a memory device is provided. The method for fabricating a memory device includes forming a first dielectric layer over a substrate and...
2018/0145141 SPATIALLY DECOUPLED FLOATING GATE SEMICONDUCTOR DEVICE
A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a...
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