Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0189235 CALIBRATION OF A CHEST-MOUNTED WIRELESS SENSOR DEVICE FOR POSTURE AND ACTIVITY DETECTION
A method and system for calibrating a wireless sensor device are disclosed. In a first aspect, the method comprises determining a vertical calibration vector...
2018/0189234 HARDWARE ACCELERATOR ARCHITECTURE FOR PROCESSING VERY-SPARSE AND HYPER-SPARSE MATRIX DATA
An accelerator architecture for processing very-sparse and hyper-sparse matrix data is disclosed. A hardware accelerator comprises one or more tiles, each...
2018/0189233 INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY
Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One...
2018/0189232 METHOD AND APPARATUS TO BUILD A MONOLITHIC MESH INTERCONNECT WITH STRUCTURALLY HETEROGENOUS TILES
A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with...
2018/0189231 PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder...
2018/0189230 PROCESSOR IN NON-VOLATILE STORAGE MEMORY
In one example, a device includes a non-volatile memory divided into a plurality of selectable locations, wherein the selectable locations are grouped into a...
2018/0189229 DEEP CONVOLUTIONAL NETWORK HETEROGENEOUS ARCHITECTURE
Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus,...
2018/0189228 GUIDED MACHINE-LEARNING TRAINING USING A THIRD PARTY CLOUD-BASED SYSTEM
Systems and methods may enable a user who may not have any experience in machine learning to effectively train new models for use in object recognition...
2018/0189227 DIMENSION SHUFFLING USING MATRIX PROCESSORS
In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data...
2018/0189226 MEDIA CONTENT PLAYBACK WITH STATE PREDICTION AND CACHING
Systems, devices, apparatuses, components, methods, and techniques for predicting user and media-playback device states are provided. Systems, devices,...
2018/0189225 SYSTEM AND METHOD FOR IMPROVING PERIPHERAL COMPONENT INTERFACE EXPRESS BUS PERFORMANCE IN AN INFORMATION...
An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory...
2018/0189224 APPARATUSES FOR PERIODIC UNIVERSAL SERIAL BUS (USB) TRANSACTION SCHEDULING AT FRACTIONAL BUS INTERVALS
Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus...
2018/0189223 UNIVERSAL SERIAL BUS TYPE-C POWER DELIVERY
In some examples, a power delivery system includes a primary power path to provide power to a computing system. The power delivery system also includes a...
2018/0189222 APPARATUSES AND METHODS FOR MULTILANE UNIVERSAL SERIAL BUS (USB2) COMMUNICATION OVER EMBEDDED UNIVERSAL SERIAL...
Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus...
2018/0189221 POSITIONALLY AWARE COMMUNICATION WITH MULTIPLE STORAGE DEVICES OVER A MULTI-WIRE SERIAL BUS
Apparatuses, systems, and methods having positionally aware communication between a controller and a plurality of solid state drives (SSD) over a multi-wire...
2018/0189220 SYNCHRONOUS TRANSMISSION DEVICE AND SYNCHRONOUS TRANSMISSION METHOD
A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is...
2018/0189219 METHOD OF RECONFIGURING DQ PADS OF MEMORY DEVICE AND DQ PAD RECONFIGURABLE MEMORY DEVICE
A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit...
2018/0189218 MEMORY DRIVE ADAPTERS AND MEMORY DRIVE UNITS INCORPORATING THE SAME
Technology is provided for a memory drive adapter. The memory drive adapter is used for combining memory drives within an alternative form factor. For example...
2018/0189217 TECHNIQUES FOR AN EXTENDABLE PERIPHERAL PORT
Various embodiments may be generally directed to techniques for an extendable peripheral port. Some embodiments are particularly directed to a computing...
2018/0189215 RECONFIGURABLE INTERCONNECT
Embodiments are directed towards a reconfigurable stream switch formed in an integrated circuit. The stream switch includes a plurality of output ports, a...
2018/0189214 CROSSTALK CANCELLATION TRANSMISSION BRIDGE
Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a...
2018/0189213 ADAPTIVE CALIBRATION TECHNIQUE FOR CROSS TALK CANCELLATION
Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the...
2018/0189212 MULTI-SENSING USING MULTIPLE SERIAL PROTOCOLS OVER A COMMON INTERCONNECTION SCHEME
A multi-sensing system (20) includes multiple sensor units (28) that include respective sensors (44), (ii) are connected to one another in a cascade using...
2018/0189211 SYSTEMS AND METHODS OF ADJUSTING AN INTERFACE BUS SPEED
A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay...
2018/0189210 INTEGRATED CIRCUIT INPUTS AND OUTPUTS
An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one...
2018/0189209 DELAY CONTROL DEVICE, DELAY CONTROL METHOD AND ELECTRONIC APPARATUS
A delay control device, a delay control method and an electronic apparatus are provided. The delay control device includes: a trigger port, configured to...
2018/0189208 SYSTEM AND METHOD FOR AUTONOMOUS TIME-BASED DEBUGGING
A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a...
2018/0189207 MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first...
2018/0189206 SEMICONDUCTOR SYSTEM INCLUDING HETEROGENEOUS MEMORY MODULE
A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory...
2018/0189205 SYSTEM AND METHOD FOR OPERATING A MICROCONTROLLER
An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the...
2018/0189204 COMPUTER PROGRAM PRODUCT, SYSTEM, AND METHOD TO ALLOW A HOST AND A STORAGE DEVICE TO COMMUNICATE BETWEEN...
Provided are a computer program product, method, and system to transfer storage input/output (I/O) requests to host and target systems on different fabrics. An...
2018/0189203 VARIABLE ACQUISITION BUFFER LENGTH
A system and method for determining an acquisition buffer size for use in processing signals, the method including determining a number of samples obtained for...
2018/0189202 SYSTEM MEMORY HAVING POINT-TO-POINT LINK THAT TRANSPORTS COMPRESSED TRAFFIC
An apparatus is described. The apparatus includes a main memory controller having a point-to-point link interface to couple to a point-to-point link. The...
2018/0189201 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS)...
2018/0189200 MEMORY SYSTEM AND OPERATION METHOD OF THE SAME
A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory...
2018/0189199 SYSTEMS AND METHODS FOR LOW LATENCY ACCESS OF MEMORY BETWEEN COMPUTING DEVICES
Disclosed are methods and systems for low latency modification of memory on a remote computer system. According to one aspect of the present disclosure, a...
2018/0189198 METHOD FOR PERFORMING COMMUNICATION BETWEEN PERIPHERAL DEVICES OF MOBILE TERMINAL AND MOBILE TERMINAL
The embodiments of the disclosure disclose a communication method between peripheral devices of a mobile terminal and a mobile terminal. The mobile terminal...
2018/0189197 KEYBOARD-VIDEO-MOUSE SWITCH, AND SIGNAL TRANSMITTING METHOD
A KVM switch is disclosed. The KVM switch, for connecting between computers and at least one peripheral device, the KVM switch includes a first interface,...
2018/0189196 COMMUNICATION METHOD AND MOBILE TERMINAL
The embodiments of the disclosure disclose a communication method and a mobile terminal. The method includes: when a data communication request sent from a...
2018/0189195 NON-VOLATILE RANDOM ACCESS MEMORY WITH GATED SECURITY ACCESS
Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a...
2018/0189194 VIRTUAL ROOT OF TRUST FOR DATA STORAGE DEVICE
A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) including a private partition with a write-once partition only internally accessed by a...
2018/0189193 PERIODICALLY RE-ENCRYPTING USER DATA STORED ON A STORAGE DEVICE
Periodically re-encrypting user data stored on a storage device, including: reading user data stored on the storage device, wherein the user data is associated...
2018/0189192 MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND MEMORY CONTROLLER THAT SUPPORTS CONCURRENT...
An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache...
2018/0189191 MULTI-LEVEL PAGING AND ADDRESS TRANSLATION IN A NETWORK ENVIRONMENT
An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory...
2018/0189190 Controlling Access to Pages in a Memory in a Computing Device
A computing device that handles address translations is described. The computing device includes a hardware table walker and a memory that stores a reverse map...
2018/0189189 IMPLEMENTING PAGING DEVICE SELECTION BASED ON WEAR-LEVEL DATA
A method, system and computer program product for implementing paging device selection based on wear-level factor data in a computer system. Paging is used to...
2018/0189188 UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY
Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein...
2018/0189187 RECOVERY OF VALIDITY DATA FOR A DATA STORAGE SYSTEM
The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into...
2018/0189186 POWER AND PERFORMANCE-EFFICIENT CACHE DESIGN FOR A MEMORY ENCRYPTION ENGINE
Apparatuses, systems, and methods for hardware-level data encryption having integrity and replay protection are described. An example electronic device...
2018/0189185 MEDIA CACHE BAND CLEANING
A data storage device includes a media cache and a main data store optimized for sequential reads and organized into bands. When the data storage device...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.