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Patent # Description
2019/0067340 THIN FILM TRANSISTOR AND DISPLAY SUBSTRATE, FABRICATION METHOD THEREOF, AND DISPLAY DEVICE
A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a...
2019/0067339 ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF AND DISPLAY PANEL
An array substrate and a fabrication method thereof and a display panel are provided. The array substrate including a first thin film transistor and a second...
2019/0067338 Amoled Substrate and Method for Manufacturing Same
The present disclosure provides a method for manufacturing an AMOLED substrate and an AMOLED substrate. The method includes the steps of: providing a base...
2019/0067337 Display substrate, manufacture method thereof, and display device
Disclosed are a display substrate, a manufacture method thereof, and a display device. The display substrate comprises: a base substrate, and a metal layer, at...
2019/0067336 SEMICONDUCTOR DISPLAY DEVICE
It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface...
2019/0067335 MANUFACTURING METHOD OF PIXEL STRUCTURE
A method for manufacturing a pixel structure is provided. A patterned semiconductor material layer, an insulation material layer, and a gate electrode material...
2019/0067334 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT...
2019/0067333 DISPLAY DEVICE
A display device includes a signal line driver, provided in a peripheral area of a display panel, that outputs video signals, a signal selection circuit that...
2019/0067332 Array Substrate and Method for Manufacturing the Same, Display Device
The present disclosure provides an array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes a base...
2019/0067331 DISPLAY PANEL, PRODUCTION METHOD OF THE SAME, AND DISPLAY APPARATUS
This disclosure discloses a display panel, a production method thereof, and a display apparatus. This method comprises: forming a pattern of a first metal...
2019/0067330 ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality...
2019/0067329 ARRAY SUBSTRATE AND DRIVING METHOD THEREOF, DISPLAY DEVICE
An array substrate, a driving method thereof and a display device are provided. The array substrate includes a base substrate, a pixel electrode located on the...
2019/0067328 ARRAY SUBSTRATE AND DISPLAY DEVICE
An array substrate includes a display region and a non-display region arranged adjacent to the display region. A plurality of signal connection lines is...
2019/0067327 Staggered Word Line Architecture for Reduced Disturb in 3-Dimensional NOR Memory Arrays
A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance...
2019/0067326 MEMORY DEVICES INCLUDING VERTICAL MEMORY CELLS AND RELATED METHODS
Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory...
2019/0067325 NOR FLASH MEMORY
A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present...
2019/0067324 METHOD FOR FORMING A THREE-DIMENSIONAL MEMORY DEVICE
Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a...
2019/0067323 METHOD FOR FORMING GATE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE
A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating dielectric stack on a substrate; forming...
2019/0067322 Three-Dimensional Memory Device and Fabricating Method Thereof
Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess...
2019/0067321 VERTICAL MEMORY DEVICE
A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate...
2019/0067320 SEMICONDUCTOR DEVICE INCLUDING STACK STRUCTURE AND TRENCHES
A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed...
2019/0067319 MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second...
2019/0067318 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, the substrate includes a plurality of protrusions having columnar configurations, and a void being formed below the protrusions....
2019/0067317 SEMICONDUCTOR DEVICE
According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the...
2019/0067316 WIRING LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the...
2019/0067315 THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction...
2019/0067314 INTERCONNECT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE
Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an...
2019/0067313 METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a...
2019/0067312 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the...
2019/0067311 MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second...
2019/0067310 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal material inside the first holes; forming a...
2019/0067309 Method for Forming a PN Junction and Associated Semiconductor Device
An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the...
2019/0067308 NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral...
2019/0067307 NON-VOLATILE MEMORY WITH RESTRICTED DIMENSIONS
A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each...
2019/0067306 SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CARBON-DOPED SILICON NITRIDE AND RELATED METHODS
A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers...
2019/0067305 SEMICONDUCTOR STRUCTURE FOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME
A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the...
2019/0067303 Methods Used In Forming An Array Of Memory Cells
In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming...
2019/0067302 HIGH-K METAL GATE (HKMG) PROCESS FOR FORMING A MEMORY CELL WITH A LARGE OPERATION WINDOW
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high...
2019/0067301 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second...
2019/0067300 METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS
In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that...
2019/0067299 USING THREE OR MORE MASKS TO DEFINE CONTACT-LINE-BLOCKING COMPONENTS IN FINFET SRAM FABRICATION
A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns...
2019/0067298 Apparatuses Having Memory Cells with Two Transistors and One Capacitor, and Having Body Regions of the...
Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor...
2019/0067297 METHOD FOR MANUFACTURING A MICROELECTRONIC CIRCUIT AND CORRESPONDING MICROELECTRONIC CIRCUIT
The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact...
2019/0067296 BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first...
2019/0067295 MULTI-COMPONENT CONDUCTIVE STRUCTURES FOR SEMICONDUCTOR DEVICES
Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a...
2019/0067294 SEMICONDUCTOR DEVICE
A first bit line structure is disposed between a first contact structure and a second contact structure. A first air spacer is interposed between the first...
2019/0067293 BURIED WORD LINE STRUCTURE AND METHOD OF MAKING THE SAME
A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are...
2019/0067292 INSULATING STRUCTURE AND METHOD OF FORMING THE SAME
A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask...
2019/0067291 INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, AND ITS FABRICATING PROCESS
A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an...
2019/0067290 Buried Metal Track and Methods Forming Same
An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a...
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