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Patent # Description
2019/0067239 NON-POROUS COPPER TO COPPER INTERCONNECT
A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having...
2019/0067238 METHODS AND SYSTEMS FOR INHIBITING BONDING MATERIALS FROM CONTAMINATING A SEMICONDUCTOR PROCESSING TOOL
Methods and systems for inhibiting bonding materials from entering a vacuum system of a semiconductor processing tool are disclosed herein. A semiconductor...
2019/0067237 METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC DEVICE USING DEVICE CHIP
[Object] To provide a method and an apparatus for manufacturing electronic devices by transferring the device chips from one substrate for producing device...
2019/0067236 CHIP PACKAGING STRUCTURE AND PACKAGING METHOD
A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of...
2019/0067235 METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a...
2019/0067234 ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF
An anisotropic conductive film 1A includes a conductive particle array layer 4 in which a plurality of conductive particles 2 are arrayed in a prescribed...
2019/0067233 HIGH-YIELD SEMICONDUCTOR DEVICE MODULES AND RELATED SYSTEMS
Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first...
2019/0067232 Method for Solder Bridging Elimination for Bulk Solder C2S Interconnects
A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between...
2019/0067231 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface...
2019/0067230 ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME
An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die...
2019/0067229 Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices
A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one...
2019/0067228 SEMICONDUCTOR DEVICE
A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed...
2019/0067227 FAN-OUT SEMICONDUCTOR PACKAGE
A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the...
2019/0067226 INTEGRATED CIRCUIT COMPONENT PACKAGE AND METHOD OF FABRICATING THE SAME
An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality...
2019/0067225 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor...
2019/0067224 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first wiring structure. The first wiring structure has a first insulation layer including a reinforcement material. A first...
2019/0067223 RADAR MODULE WITH WAFER LEVEL PACKAGE AND UNDERFILL
A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package...
2019/0067222 SEMICONDUCTOR STRUCTURE
A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of...
2019/0067221 HIGH ASPECT RATIO INTERCONNECTS IN AIR GAP OF ANTENNA PACKAGE
In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the...
2019/0067220 PACKAGE STRUCTURE AND METHOD OF FABRICATING PACKAGE STRUCTURE
A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit...
2019/0067219 ANTENNA-ON-PACKAGE ARRANGEMENTS
An package and related methods are disclosed. The package may include an antenna, an insert made of low-loss material, and a mold, wherein the mold directly...
2019/0067218 THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE
A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan...
2019/0067217 METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING
One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation...
2019/0067216 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DICE INCLUDING ELECTRICALLY CONDUCTIVE INTERCONNECTS BETWEEN DIE RINGS
A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises...
2019/0067215 TRENCH STRUCTURE AND METHOD
A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first...
2019/0067214 SEMICONDUCTOR DEVICE
A semiconductor device includes a heat dissipating unit that includes a primary part made of a first metal material and an embedded part that is embedded in a...
2019/0067212 PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die...
2019/0067211 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface...
2019/0067210 SEAL RING STRUCTURE OF INTEGRATED CIRCUIT AND METHOD OF FORMING SAME
A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first...
2019/0067209 Compressive Interlayer Having a Defined Crack-Stop Edge Extension
A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the...
2019/0067208 CIRCUIT BOARD AND CHIP PACKAGE
A chip package includes a circuit board, an encapsulation, a plurality of conductive structures and an electromagnetic interference (EMI) protection layer. The...
2019/0067207 SEMICONDUCTOR PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at...
2019/0067206 APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE
Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end...
2019/0067205 THERMAL AND ELECTROMAGNETIC INTERFERENCE SHIELDING FOR DIE EMBEDDED IN PACKAGE SUBSTRATE
A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package...
2019/0067204 ALIGNMENT MARK AND MEASUREMENT METHOD THEREOF
The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy...
2019/0067203 SEMICONDUCTOR METROLOGY TARGET AND MANUFACTURING METHOD THEREOF
A metrology target of a semiconductor device is provided. The metrology target includes a substrate including first and second layers. The first layer includes...
2019/0067202 Electrically Conductive Laminate Structures
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
2019/0067201 SEED LAYERS FOR COPPER INTERCONNECTS
Methods for forming a copper seed layer having improved anti-migration properties are described herein. In one embodiment, a method includes forming a first...
2019/0067200 STRUCTURE FOR STACKED LOGIC PERFORMANCE IMPROVEMENT
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an...
2019/0067199 WIRING BOARD AND ELECTRONIC DEVICE
A wiring board includes: a connection pad; an insulating layer that covers the connection pad and has an opening portion exposing a portion of the connection...
2019/0067198 LOW RESISTANCE CONTACTS INCLUDING INTERMETALLIC ALLOY OF NICKEL, PLATINUM, TITANIUM, ALUMINUM AND TYPE IV...
A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti)...
2019/0067197 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF
Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the...
2019/0067196 METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front...
2019/0067195 Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch...
Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one...
2019/0067194 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF
Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the...
2019/0067193 Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch...
Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one...
2019/0067192 Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch...
Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced...
2019/0067191 HYBRID MATERIAL ELECTRICALLY PROGRAMMABLE FUSE AND METHODS OF FORMING
Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse...
2019/0067190 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive...
2019/0067189 LAYOUT TECHNIQUE FOR MIDDLE-END-OF-LINE
In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain...
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