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Patent # Description
2019/0067188 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or...
2019/0067187 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONDUCTIVE FEATURES
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2019/0067186 SEMICONDUCTOR DEVICES INCLUDING CAPACITORS, RELATED ELECTRONIC SYSTEMS, AND RELATED METHODS
A semiconductor device includes a capacitor structure. The capacitor structure comprises conductive vias extending through openings in a stack of alternating...
2019/0067185 Semiconductor Device and Layout Design Thereof
A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A...
2019/0067184 INTERCONNECT STRUCTURE
An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top...
2019/0067183 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, and a plurality of bit lines. The semiconductor substrate includes...
2019/0067182 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a wiring structure, a stacked structure located over the wrong structure, channel structures passing through the stacked...
2019/0067181 SEMICONDUCTOR PACKAGES
A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to...
2019/0067180 ELECTRONIC DEVICE INCLUDING AT LEAST ONE ELECTRONIC CHIP AND ELECTRONIC PACKAGE
An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer...
2019/0067179 Semiconductor Device and Method of Manufacture
A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the porous dielectric layer, and a first hardmask is formed over the...
2019/0067178 FINE PITCH AND SPACING INTERCONNECTS WITH RESERVE INTERCONNECT PORTION
Some features pertain to a substrate that includes a first dielectric, a first interconnect, and a second interconnect. The first interconnect is at least...
2019/0067177 SEMICONDUCTOR DEVICE
A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the...
2019/0067176 VOID REDUCTION IN SOLDER JOINTS USING OFF-EUTECTIC SOLDER
Embodiments herein may relate to an apparatus with a package that includes a first substrate soldered to a second substrate via solder comprising an...
2019/0067175 MOLDED INTELLIGENT POWER MODULE AND METHOD OF MAKING THE SAME
An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor...
2019/0067174 Packaged Fast Inverse Diode Component For PFC Applications
A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package...
2019/0067173 TAPE CARRIER ASSEMBLIES HAVING AN INTEGRATED ADHESIVE FILM
Introduced here are carrier tape assemblies that can improve efficiency and reduce costs when utilized in the handling, transport, or storage of semiconductor...
2019/0067172 PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING
A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side,...
2019/0067171 ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION
In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface...
2019/0067170 SURFACE MOUNTED TYPE LEADFRAME AND PHOTOELECTRIC DEVICE WITH MULTI-CHIPS
A surface mounted type leadframe includes a conductive base and an insulating material layer. The conductive base includes at least three connecting pads...
2019/0067169 SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution...
2019/0067168 CHIP ON FILM PACKAGE AND MANUFACTURING METHOD OF CHIP ON FILM PACKAGE
A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second...
2019/0067167 COMPONENT STRUCTURE, POWER MODULE AND POWER MODULE ASSEMBLY STRUCTURE
The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component...
2019/0067166 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor device including a connection terminal that is electrically connected to a semiconductor chip, a bus bar with an opening through which the...
2019/0067165 POWER MODULE AND METHOD OF MANUFACTURING THE SAME, AND POWER ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING...
A power module includes a first power semiconductor device including a first electrode, a resin frame including first receiving portions, and a first...
2019/0067164 INTEGRATED PASSIVE DEVICE AND FABRICATION METHOD USING A LAST THROUGH-SUBSTRATE VIA
In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a...
2019/0067163 PARTIALLY MOLDED DIRECT CHIP ATTACH PACKAGE STRUCTURES FOR CONNECTIVITY MODULE SOLUTIONS
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a...
2019/0067162 METHODS AND SYSTEMS FOR HIGH VOLTAGE COMPONENT COOLING IN ELECTRIC VEHICLE FOR FAST CHARGE
Methods and systems are disclosed for controlling heat within a junction box. The disclosure relates to the use of phase change materials to manage heat...
2019/0067161 SEMICONDUCTOR LASER MODULE AND METHOD FOR MANUFACTURING THE SAME
The semiconductor laser module 1 has an electrically conductive heat sink 10, a submount 20 disposed above the heat sink 10, a semiconductor laser device 30...
2019/0067160 POWER MODULE WITH MULTI-LAYER SUBSTRATE
A power system has a single-side-cooled power module including a contiguous five-layer substrate of two insulative layers interleaved with three conductive...
2019/0067159 SEMICONDUCTOR DEVICE
In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on...
2019/0067157 Heat Spreading Device and Method
In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die...
2019/0067156 SEMICONDUCTOR PACKAGE WITH THERMAL FINS
Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments....
2019/0067155 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A semiconductor structure includes a substrate. The substrate includes a plurality of function regions and a plurality of heat-dissipation regions. Each...
2019/0067154 POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD
The power module of the invention includes a power element, a metal base for dissipating heat from the power element, a lead frame electrically connected to...
2019/0067153 HEAT SPREADER EDGE STANDOFFS FOR MANAGING BONDLINE THICKNESS IN MICROELECTRONIC PACKAGES
A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic...
2019/0067152 ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device...
2019/0067151 THREE-DIMENSIONAL PACKAGING STRUCTURE AND PACKAGING METHOD OF POWER DEVICES
A three-dimensional packaging structure and a packaging method of power devices. The packaging structure includes power devices, direct copper bonded...
2019/0067150 DEVICES AND METHODS FOR HEAT DISSIPATION OF SEMICONDUCTOR INTEGRATED CIRCUITS
A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two...
2019/0067149 PLANAR PASSIVATION LAYERS
A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first...
2019/0067148 Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same
A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a...
2019/0067147 FIBER-CONTAINING RESIN SUBSTRATE, ENCAPSULATED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, ENCAPSULATED...
A fiber-containing resin substrate includes a thermosetting epoxy resin-impregnated fiber base material, and an uncured resin layer formed on one side thereof...
2019/0067146 Non-Vertical Through-via in Package
A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein...
2019/0067145 SEMICONDUCTOR DEVICE
A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the...
2019/0067144 INTEGRATED FAN-OUT PACKAGE, PACKAGE-ON-PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF
An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second ...
2019/0067143 MOLDED WAFER LEVEL PACKAGING
In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical...
2019/0067142 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a...
2019/0067141 AIR CAVITY MOLD
Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To...
2019/0067140 PACKAGE STRUCTURE AND ITS FABRICATION METHOD
A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer...
2019/0067139 Integrated Circuit Package with Stress Directing Material
An encapsulated integrated circuit that includes an integrated circuit (IC) die and an encapsulation material encapsulating the IC die. A first portion of the...
2019/0067138 METHOD TO DECREASE FLICKER NOISE IN CONDUCTOR-INSULATOR-SEMICONDUCTOR (CIS) DEVICES
A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate,...
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