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Patent # Description
2019/0067137 SEMICONDUCTOR DEVICE WITH A PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top...
2019/0067136 STACKED SEMICONDUCTOR APPARATUS BEING ELECTRICALLY CONNECTED THROUGH THROUGH-VIA AND MONITORING METHOD
A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of...
2019/0067135 APPARATUS FOR INSPECTION OF A PACKAGE ASSEMBLY WITH A THERMAL SOLUTION
Embodiments of the present disclosure provide techniques and configurations for inspection of a package assembly with a thermal solution, in accordance with...
2019/0067134 METHOD OF EXAMINING DEFECTS IN A SEMICONDUCTOR SPECIMEN AND SYSTEM THEREOF
There is provided a method of examining defects in a semiconductor specimen and a system thereof. The method comprises: processing a first defect map obtained...
2019/0067133 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Semiconductor layer is formed on semiconductor substrate. Semiconductor layer has a plurality of well regions in a surface remote from semiconductor substrate....
2019/0067132 METHOD FOR LITHOGRAPHIC PROCESS AND LITHOGRAPHIC SYSTEM
A method for performing a lithographic process over a semiconductor wafer is provided. The method includes coating a photoresist layer over a material layer...
2019/0067131 Interconnect Structure For Fin-Like Field Effect Transistor
Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect...
2019/0067130 Method for Source/Drain Contact Formation in Semiconductor Devices
A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D)...
2019/0067129 METHOD FOR FORMING SEMICONDUCTOR DEVICE AND RESULTING DEVICE
A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a...
2019/0067128 FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD
A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second...
2019/0067127 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a...
2019/0067126 USING A METAL-CONTAINING LAYER AS AN ETCHING STOP LAYER AND TO PATTERN SOURCE/DRAIN REGIONS OF A FINFET
A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure...
2019/0067125 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate...
2019/0067124 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH ISOLATION FEATURE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate...
2019/0067123 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A method for fabricating a semiconductor structure includes forming a plurality of first gate structures on a first region of a substrate, a plurality of...
2019/0067122 Semiconductor Device and Method
Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material...
2019/0067121 SEMICONDUCTOR DEVICE STRUCTURE WITH SEMICONDUCTOR WIRE
Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first...
2019/0067120 SELF-ALIGNED STRUCTURE FOR SEMICONDUCTOR DEVICES
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned...
2019/0067119 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The...
2019/0067118 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second...
2019/0067117 Structure and Method for Metal Gates with Roughened Barrier Layer
A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer;...
2019/0067116 LEAKAGE REDUCTION METHODS AND STRUCTURES THEREOF
A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell...
2019/0067115 GATE CUT METHOD FOR REPLACEMENT METAL GATE
A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with an etch...
2019/0067114 SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a...
2019/0067113 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate...
2019/0067112 Fin Critical Dimension Loading Optimization
Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region...
2019/0067111 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH DUMMY FIN STRUCTURE AND METHOD FOR FORMING THE SAME
A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure...
2019/0067110 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact...
2019/0067109 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer,...
2019/0067108 CUTTING APPARATUS AND GROOVE DETECTING METHOD
A cutting apparatus includes a cutting unit configured to cut a workpiece held on a chuck table, and a groove detecting unit including a CCD imaging element...
2019/0067107 METHOD OF MAKING A SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS
A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner...
2019/0067106 METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a...
2019/0067105 METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first...
2019/0067104 CONDUCTIVE VIAS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the...
2019/0067103 METHODS OF PRODUCING SELF-ALIGNED GROWN VIA
Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a...
2019/0067102 Methods Of Producing Self-Aligned Vias
Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first...
2019/0067101 BURIED CONTACT TO PROVIDE REDUCED VFET FEATURE-TO-FEATURE TOLERANCE REQUIREMENTS
Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active...
2019/0067099 Methods for Reducing Contact Depth Variation in Semiconductor Fabrication
A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure,...
2019/0067098 DOUBLE BARRIER LAYER SETS FOR CONTACTS IN SEMICONDUCTOR DEVICE
Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a...
2019/0067097 Method and IC Design with Non-Linear Power Rails
The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions,...
2019/0067096 Etching to Reduce Line Wiggling
A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first...
2019/0067095 LAYER FORMING METHOD
There is provided a method of forming a layer, comprising depositing a seed layer on the substrate; and depositing a bulk layer on the seed layer. Depositing...
2019/0067094 METHODS FOR DEPOSITING A MOLYBDENUM METAL FILM OVER A DIELECTRIC SURFACE OF A SUBSTRATE BY A CYCLICAL...
Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may...
2019/0067093 Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof
Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes...
2019/0067092 MODULATING METAL INTERCONNECT SURFACE TOPOGRAPHY
A metal interconnect structure can be fabricated within an integrated circuit (IC). A recess can be created in an IC dielectric layer and a surface modulation...
2019/0067091 TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL
A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the...
2019/0067090 Interconnect Structure and Method of Forming the Same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a...
2019/0067089 STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first...
2019/0067088 Semiconductor Device and Method of Manufacture
An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the...
2019/0067087 DUAL-DAMASCENE FORMATION WITH DIELECTRIC SPACER AND THIN LINER
A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a...
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