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Patent # Description
2019/0066833 SYSTEM AND METHOD FOR MONITORING PHYSICAL THERAPY
Various embodiments of the invention are directed to a system and method of providing physical therapy to a patient. In another embodiment, the present...
2019/0066832 METHOD FOR DETECTING PATIENT RISK AND SELECTIVELY NOTIFYING A CARE PROVIDER OF AT-RISK PATIENTS
One variation of a method for tracking patient recovery during a physical therapy program includes: assigning a recovery plan to a patient, the recovery plan...
2019/0066831 MEDICAL DEVICES AND RELATED EVENT PATTERN PRESENTATION METHODS
Medical devices and related patient management systems and methods are provided. A method of presenting information pertaining to operation of a medical device...
2019/0066830 COMPUTER SYSTEM AND METHOD FOR GENERATING TRIGGER ALERTS TO MAXIMIZE INTERACTIONS WITH HEALTHCARE PROVIDERS
A pharmaceutical company may employ a computer system that is configured to analyze anonymized patient data for patients treated by each of a plurality of...
2019/0066829 System and Method for Populating and Processing Prescription Scripts
A system and method for populating and processing prescription scripts to reduce human error and save time while filling prescriptions. A pharmacy e-pad and a...
2019/0066828 Cabinet for Dispensing Items
A cabinet that can control the distribution of products that can optionally include medications. The cabinet can have a user interface that receives...
2019/0066827 MEDICAL INFORMATION PROCESSING SYSTEM
A medical information processing system comprises a memory and processing circuitry. The memory is configured to store therein pieces of first medical data...
2019/0066826 AUGMENTED REALITY WITH REALTIME INTERACTIVE ANALYSIS METHOD AND SYSTEM THEREOF
An augmented reality with real-time interactive analysis method and a system thereof are provided. The method includes: starting an application from a portable...
2019/0066825 MEDICAL INFORMATION PROVIDING SYSTEM, SERVER, MEDICAL INFORMATION PROVIDING APPARATUS, MEDICAL INFORMATION...
A medical information providing system 1 includes a medication examination information extracting unit 21d and a database management unit 21e in a medication...
2019/0066824 PATIENT TEST DATA PROCESSING SYSTEM AND METHOD
A method at a server system for processing patient test data to provide a more automated method of inputting point of care test data into an electronic health...
2019/0066823 Automated Clinical Documentation System and Method
A method, computer program product, and computing system for functionality module communication is executed on a computing device and includes obtaining...
2019/0066822 SYSTEM AND METHOD FOR CLINICAL TRIAL MANAGEMENT
The present invention relates to computing devices, microcontrollers, memory storage devices, executable codes, methods, application software, automated voice...
2019/0066821 AUTOMATED CLINICAL DOCUMENTATION SYSTEM AND METHOD
A method, computer program product, and computing system for synchronizing machine vision and audio is executed on a computing device and includes obtaining...
2019/0066820 METHOD FOR TESTING MRAM DEVICE AND TEST APPARATUS THEREOF
The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes...
2019/0066819 REPAIR FUSE LATCHES USING STATIC RANDOM ACCESS MEMORY ARRAY
Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage...
2019/0066818 DETERMINATION OF FAST TO PROGRAM WORD LINES IN NON-VOLATILE MEMORY
Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an...
2019/0066817 ERASE PAGE CHECK
Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to...
2019/0066816 SEMICONDUCTOR MEMORY DEVICE
Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory...
2019/0066815 APPARATUS AND METHOD FOR MEASURING PERFORMANCE OF MEMORY ARRAY
The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus...
2019/0066814 Memory with a Controllable I/O Functional Unit
A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit...
2019/0066813 TESTING MEMORY CELLS
A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If...
2019/0066812 TDDB PERCOLATION CURRENT INDUCED E-FUSE STRUCTURE AND METHOD OF PROGRAMMING SAME
An e-fuse structure including a circuit having an e-fuse operably coupling the circuit to a power source, and a redundant circuit for operably coupling the...
2019/0066811 MANAGING REFRESH FOR FLASH MEMORY
Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to...
2019/0066810 VOLTAGE DEGRADATION AWARE NAND ARRAY MANAGEMENT
Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage...
2019/0066809 READ DISTURB DETECTION AND RECOVERY WITH ADAPTIVE THRESHOLDING FOR 3-D NAND STORAGE
A system includes memory cells arranged in blocks and a memory controller. The memory controller receives a read command to read a first block. The first block...
2019/0066808 PER ROW ACTIVATION COUNT VALUES EMBEDDED IN STORAGE CELL ARRAY STORAGE CELLS
A DRAM memory having a storage cell array is described. The storage cell array has rows and columns. The storage cell array has reserved storage cells coupled...
2019/0066807 RESPONDING TO POWER LOSS
Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a...
2019/0066806 SEMICONDUCTOR DEVICE HAVING RING OSCILLATOR AND METHOD OF ARRANGING RING OSCILLATOR
A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink...
2019/0066805 Sense Amplifier Circuit For Reading Data In A Flash Memory Cell
Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or...
2019/0066804 DETERMINING DATA STATES OF MEMORY CELLS
Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in...
2019/0066803 MEMORY SYSTEM WITH ADAPTIVE READ-THRESHOLD SCHEME AND METHOD OF OPERATING SUCH MEMORY SYSTEM
Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads...
2019/0066802 READ VOLTAGE CALIBRATION BASED ON HOST IO OPERATIONS
Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device...
2019/0066801 CHARACTERIZING AND OPERATING A NON-VOLATILE MEMORY DEVICE
A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are...
2019/0066800 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: a nonvolatile memory device including a plurality of memory blocks; and a controller suitable for dividing the plurality of memory...
2019/0066799 SECURE ERASE FOR DATA CORRUPTION
Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that...
2019/0066798 ERASING MEMORY CELLS
Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected...
2019/0066797 ERASING MEMORY CELLS
Methods include applying a first voltage to channel regions of a plurality of memory cells; applying a lower second voltage to each access line of a plurality...
2019/0066795 FAST PROGRAMMING METHODS FOR FLASH MEMORY DEVICES
A byte-programming method for programming data from a page register to a non-volatile memory array includes reading data of a selected byte in the page...
2019/0066794 MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM
A memory system may include a memory controller transferring first and second logical page data to a memory device, wherein the memory device comprises a...
2019/0066793 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
A semiconductor memory device includes a memory cell array coupled to a plurality of word lines, a voltage generator generating a program voltage and first and...
2019/0066792 NAND TEMPERATURE DATA MANAGEMENT
Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at...
2019/0066791 LOG DATA STORAGE FOR FLASH MEMORY
Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be...
2019/0066790 DISTRIBUTED MODE REGISTERS IN MEMORY DEVICES
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the...
2019/0066789 WORD-LINE PRE-CHARGING IN POWER-ON READ OPERATION TO REDUCE PROGRAMMING VOLTAGE LEAKAGE
This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a...
2019/0066788 REDUCED ROUTING SIGNALS
Apparatuses, systems, methods, and computer program products are disclosed for reduced routing signals. An apparatus includes a generator circuit that...
2019/0066787 MEMORY ARCHITECTURE AND OPERATION
Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second...
2019/0066786 SENSE-LINE MUXING SCHEME
The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines...
2019/0066785 MEMORY CELL, MEMORY CELL ARRAY, MEMORY DEVICE AND OPERATION METHOD OF MEMORY CELL ARRAY
Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from...
2019/0066784 Memory Systems and Memory Programming Methods
Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a...
2019/0066783 Memory Sense Amplifiers and Memory Verification Methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
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