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Patent # Description
2019/0066782 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a...
2019/0066781 METHODS AND APPARATUS FOR MEMORY CELL END OF LIFE DETECTION AND OPERATION
A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to...
2019/0066780 LINEAR TRANSFORMATION ACCELERATORS
Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate...
2019/0066779 INTEGRATED 1T1R RRAM MEMORY CELL
One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base...
2019/0066778 PHASE CHANGE MEMORY APPARATUS AND READ CONTROL METHOD TO REDUCE READ DISTURB AND SNEAK CURRENT PHENOMENA
A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device...
2019/0066777 PER-PIN COMPACT REFERENCE VOLTAGE GENERATOR
Systems, apparatuses, and methods for generating a reference voltage are described. In various embodiments, an interface between a memory and a processor uses...
2019/0066776 MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM
According to one embodiment, a memory system comprising: a semiconductor storage device including a memory cell connected to a word line and capable of storing...
2019/0066775 REFLOW PROTECTION
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received...
2019/0066774 Write Assist for a Memory Device and Methods of Forming the Same
A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit...
2019/0066773 MEMORY DEVICES AND METHODS OF OPERATING THE SAME
A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected...
2019/0066772 Read Assist Circuitry for Memory Applications
Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated...
2019/0066771 MEMORY ARRAY RESET READ OPERATION
Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a...
2019/0066769 Dummy Wordline Underdrive Circuitry
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy...
2019/0066768 Memory Device Comprising An Electrically Floating Body Transistor
A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI)...
2019/0066767 METHOD AND APPARATUS FOR PRECHARGE AND REFRESH CONTROL
Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device...
2019/0066766 SYSTEMS AND METHODS FOR REFRESHING A MEMORY BANK WHILE ACCESSING ANOTHER MEMORY BANK USING A SHARED ADDRESS PATH
A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a...
2019/0066765 DRAM AND METHOD FOR OPERATING THE SAME
The present disclosure provides a DRAM including a first refresh unit, a second refresh unit, and a control device. The first refresh unit has a first quantity...
2019/0066764 APPARATUSES AND METHODS FOR DATA TRANSMISSION OFFSET VALUES IN BURST TRANSMISSIONS
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset...
2019/0066763 CHIP WITH PHASE CHANGE MEMORY AND MAGNETORESISTIVE RANDOM ACCESS MEMORY
Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus...
2019/0066762 VOLATILE MEMORY DEVICE INCLUDING STACKED MEMORY CELLS
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar...
2019/0066761 PROCESSING IN MEMORY
Apparatuses and methods are provided for processing in memory. An example apparatus includes a processing in memory (PIM) capable device having an array of...
2019/0066760 DRAM AND METHOD FOR OPERATING THE SAME
The present disclosure provides a DRAM. The DRAM includes a memory array and a control device. The memory array has a plurality of word lines configured to...
2019/0066759 ROW HAMMER MITIGATION WITH RANDOMIZATION OF TARGET ROW SELECTION
A memory device with internal row hammer mitigation includes randomization for selection of victim rows to refresh for row hammer mitigation. When memory...
2019/0066758 COMMAND SIGNAL CLOCK GATING
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is...
2019/0066757 ADJUSTING SIGNAL TIMING
Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the...
2019/0066756 MEMORY WITH TERMINATION CIRCUIT
A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and...
2019/0066755 TIME-BASED ACCESS OF A MEMORY CELL
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
2019/0066754 TIME-BASED ACCESS OF A MEMORY CELL
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
2019/0066753 SELF-REFERENCING MEMORY DEVICE
Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The...
2019/0066752 WEAR LEVELING FOR RANDOM ACCESS AND FERROELECTRIC MEMORY
Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g.,...
2019/0066751 Memory Cells and Arrays of Memory Cells
A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors...
2019/0066750 DUAL MODE MEMORY SYSTEM AND METHOD OF WORKING THE SAME
A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect...
2019/0066749 MAGNETIC MEMORY
A magnetic memory includes: first to third terminals; a conductive layer including first to fifth regions, the first region being electrically connected to the...
2019/0066748 MEMORY DEVICES CONFIGURED TO PREVENT READ FAILURE DUE TO LEAKAGE CURRENT INTO BIT LINE
A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the...
2019/0066747 METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS UTILIZING HIGH CRYSTALLIZATION TEMPERATURE-CONTAINING...
A magnetic device and method for providing the magnetic device junction are described. The magnetic device includes magnetic junctions and spin-orbit...
2019/0066746 VARYING ENERGY BARRIERS OF MAGNETIC TUNNEL JUNCTIONS (MTJs) IN DIFFERENT MAGNETO-RESISTIVE RANDOM ACCESS MEMORY...
Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to...
2019/0066745 ADJUSTING INSTRUCTION DELAYS TO THE LATCH PATH IN DDR5 DRAM
Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a...
2019/0066744 SEMICONDUCTOR STORAGE DEVICE
A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second...
2019/0066743 DECODE CIRCUITRY COUPLED TO A MEMORY ARRAY
In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode...
2019/0066742 METHODS OF DETERMINING HOST CLOCK FREQUENCY FOR RUN TIME OPTIMIZATION OF MEMORY AND MEMORY DEVICES EMPLOYING...
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to...
2019/0066741 APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS
Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider...
2019/0066740 SYSTEM AND METHOD FOR CONTROLLING PHASE ALLIGNMENT OF CLOCK SIGNALS
A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit,...
2019/0066739 OPTIMIZED SCAN INTERVAL
A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be...
2019/0066738 SEMICONDUCTOR DIES SUPPORTING MULTIPLE PACKAGING CONFIGURATIONS AND ASSOCIATED METHODS
A memory device to be placed on a substrate package is configured to operate in multiple modes and support multiple memory densities is provided. The memory...
2019/0066737 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory cell array with bit lines and word lines connected thereto. A first power supply circuit generates a selected...
2019/0066736 NAND CELL ENCODING TO IMPROVE DATA INTEGRITY
Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is...
2019/0066735 Embedding Thumbnail Information Into Video Streams
Methods and systems may provide for embedding thumbnail information into a video file such as a clip, stream, recording, and so forth. The thumbnail...
2019/0066734 IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND STORAGE MEDIUM
An image processing apparatus includes: a selection unit configured to select one operation mode from a plurality of operation modes including at least a first...
2019/0066733 CINEMATIC SPACE-TIME VIEW SYNTHESIS FOR ENHANCED VIEWING EXPERIENCES IN COMPUTING ENVIRONMENTS
A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments,...
2019/0066732 Video Skimming Methods and Systems
In an embodiment, an apparatus and method of creating a skimming preview of a video includes electronically receiving a plurality of video shots, analyzing...
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