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Patent # Description
2019/0065413 BURST-SIZED LINKED LIST ELEMENTS FOR A QUEUE
Methods, apparatus, circuitry, and systems to construct a queue including a plurality of elements are provided. A method includes receiving metadata describing...
2019/0065412 METHOD AND APPARATUS FOR ESTABLISHING CONNECTION IN NON-VOLATILE MEMORY SYSTEM
A method for establishing a connection in a non-volatile memory system is provided. A connection to a host is established. A request message with a target...
2019/0065411 SECURITY ARRANGEMENT
The present invention relates to a security arrangement comprising a data processing unit for serial transmission of data for controlling outputs and for...
2019/0065410 PERIPHERAL PROCESSING DEVICE
A peripheral processing device comprises a physical interface for connecting the processing device to a host computing device through a communications...
2019/0065409 METHOD, APPARATUS, AND COMPUTER-READABLE MEDIUM FOR IMPLEMENTATION OF A UNIVERSAL HARDWARE-SOFTWARE INTERFACE
A system, method and computer-readable medium for implementation of a universal hardware-software interface, including determining, by a virtual driver, a user...
2019/0065408 CAPABILITY ENFORCEMENT PROCESSORS
Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that...
2019/0065407 METHOD OF SECURE MEMORY ADDRESSING
Problem The problem to be solved is to seek an alternative to known addressing methods which provides the same or similar effects or is more secure. Solution The...
2019/0065406 Technology For Establishing Trust During A Transport Layer Security Handshake
In a method for protecting extra-enclave communications, a data processing system allocates a portion of random access memory (RAM) to a server application...
2019/0065405 SECURITY AWARE NON-SPECULATIVE MEMORY
Several features pertain to computing systems equipped to perform speculative processing and configured to access device memory (e.g. non-speculative or...
2019/0065404 ADAPTIVE CACHING IN A STORAGE DEVICE
Implementations described and claimed herein provide a method and system for adaptive caching in a storage device. The method includes receiving an adaptive...
2019/0065403 CUCKOO CACHING
A cuckoo cache has plural buckets of plural cells each. The cells within a bucket are ranked to approximate relative usage recency. New items can be inserted...
2019/0065402 DIRECT MEMORY ACCESS CONTROLLER, CORRESPONDING DEVICE AND METHOD FOR RECEIVING, STORING AND PROCESSING DATA
A direct memory access controller intended to be placed in a computing node of a system on chip, comprising: an input buffer for receiving packets of data to...
2019/0065401 TECHNOLOGIES FOR PROVIDING EFFICIENT MEMORY ACCESS ON AN ACCELERATOR SLED
Technologies for providing efficient access to the memory of an accelerator device include an accelerator sled. The accelerator sled includes an accelerator...
2019/0065400 APPARATUS AND METHOD FOR EFFICIENT UTILISATION OF AN ADDRESS TRANSLATION CACHE
An apparatus and method are provided for efficient utilisation of an address translation cache. The apparatus has an address translation cache with a plurality...
2019/0065399 ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAGEMENT UNIT
Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein...
2019/0065398 ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAGEMENT UNIT
Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein...
2019/0065397 METHODS OF MEMORY ADDRESS VERIFICATION AND MEMORY DEVICES EMPLOYING THE SAME
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a...
2019/0065396 METHODS OF MEMORY ADDRESS VERIFICATION AND MEMORY DEVICES EMPLOYING THE SAME
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller....
2019/0065395 STORAGE DEVICE AND DATA ARRANGEMENT METHOD
A storage device includes a nonvolatile memory and a controller configured to access the nonvolatile memory in response to a command from a host apparatus. In...
2019/0065394 METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE
The present invention provides a method for accessing a flash memory module, wherein the method includes: building a physical address to logical address (P2L)...
2019/0065393 MEMORY CONSTRAINED TRANSLATION TABLE MANAGEMENT
Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into...
2019/0065392 NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME
A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of...
2019/0065391 NONREPEATING IDENTIFIERS IN AN ADDRESS SPACE OF A NON-VOLATILE SOLID-STATE STORAGE
A method of applying an address space to data storage in a non-volatile solid-state storage is provided. The method includes receiving a plurality of portions...
2019/0065390 MULTI-SOURCE ADDRESS TRANSLATION SERVICE (ATS) WITH A SINGLE ATS RESOURCE
Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a...
2019/0065389 SYSTEM AND METHOD FOR LBA-BASED RAID
A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components....
2019/0065388 MANAGED NVM ADAPTIVE CACHE MANAGEMENT
Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The ...
2019/0065387 STORAGE SYSTEM AND METHOD FOR FAST LOOKUP IN A TABLE-CACHING DATABASE
A storage system and method for fast lookup in a table-caching database are provided. In one embodiment, a storage system is provided comprising a volatile...
2019/0065386 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a nonvolatile memory device; and a controller including a descriptor generation unit, a memory controller and a buffer unit. The...
2019/0065385 IMAGE PROCESSOR AND METHODS FOR PROCESSING AN IMAGE
A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that...
2019/0065384 EXPEDITING CACHE MISSES THROUGH CACHE HIT PREDICTION
A request to access data at a first physical address misses in a private cache of a processor. A confidence value is received for the first physical address...
2019/0065383 DIRECTLY MAPPED BUFFER CACHE ON NON-VOLATILE MEMORY
A method and apparatus for implementing a buffer cache for a persistent file system in non-volatile memory is provided. A set of data is maintained in one or...
2019/0065382 STORAGE DEVICE INITIATED COPY BACK OPERATION
Method and apparatus for managing data in a data storage system. A storage array controller device is coupled to a plurality of storage devices by an external...
2019/0065381 MAINTAINING TRACK FORMAT METADATA FOR TARGET TRACKS IN A TARGET STORAGE IN A COPY RELATIONSHIP WITH SOURCE...
Provided area computer program product, system, and method for maintaining track format metadata for target tracks in a target storage in a copy relationship...
2019/0065380 REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING EXTERNAL CACHING STRUCTURES
Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table...
2019/0065379 REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING EXTERNAL CACHING STRUCTURES
Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table...
2019/0065378 DEFERRED RESPONSE TO A PREFETCH REQUEST
Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a ...
2019/0065377 MULTI-LINE DATA PREFETCHING USING DYNAMIC PREFETCH DEPTH
A system for prefetching data for a processor includes a processor core, a memory configured to store information for use by the processor core, a cache memory...
2019/0065376 UTILIZATION-BASED THROTTLING OF HARDWARE PREFETCHERS
An system for prefetching data for a processor includes a processor core, a memory, a cache memory, and a prefetch circuit. The memory may be configured to...
2019/0065375 INTELLIGENT DATA PREFETCHING USING ADDRESS DELTA PREDICTION
A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first...
2019/0065374 PROVIDING FINE-GRAINED QUALITY OF SERVICE (QoS) CONTROL USING INTERPOLATION FOR PARTITIONED RESOURCES IN...
Providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems is disclosed. In this regard,...
2019/0065373 CACHE BUFFER
The present disclosure includes apparatuses and methods related to a cache buffer. An example apparatus can store data associated with a request in one of a...
2019/0065372 PROVIDING PRIVATE CACHE ALLOCATION FOR POWER-COLLAPSED PROCESSOR CORES IN PROCESSOR-BASED SYSTEMS
Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides...
2019/0065371 SPLIT HEAD INVALIDATION FOR CONSUMER BATCHING IN POINTER RINGS
A split head invalidation system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The...
2019/0065370 STORAGE SYSTEM AND INFORMATION PROCESSING SYSTEM FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating...
2019/0065369 INFORMATION PROCESSING APPARATUS, METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
An information processing apparatus includes a memory, and a processor coupled to the memory and configured to set, in the memory, a first region having a...
2019/0065368 MEMORY RECLAIMING METHOD AND APPARATUS
Example memory reclaiming methods and apparatuses are provided to resolve a problem that application data is lost and a restart speed of an application becomes...
2019/0065367 MEMORY DEVICE WITH DYNAMIC STORAGE MODE CONTROL
A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and...
2019/0065366 MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select...
2019/0065365 MEMORY DEVICE WITH DYNAMIC STORAGE MODE CONTROL
A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and...
2019/0065364 ALLOCATING AND CONFIGURING PERSISTENT MEMORY
Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile...
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