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Patent # Description
2019/0065212 TECHNOLOGIES FOR EFFICIENTLY BOOTING SLEDS IN A DISAGGREGATED ARCHITECTURE
Technologies for efficiently booting sleds in a disaggregated architecture include a sled. The sled includes a network interface controller, a set of...
2019/0065211 COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes,...
2019/0065210 BIOS SWITCHING DEVICE
A BIOS switching device adapted to a server comprises a switching module, a CPLD, a storage module and a BMC. The switching module comprises a movable...
2019/0065209 BYTE AND NIBBLE SORT INSTRUCTIONS THAT PRODUCE SORTED DESTINATION REGISTER AND DESTINATION INDEX MAPPING
A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an...
2019/0065208 PROCESSING DEVICE AND RELATED PRODUCTS
A processing device and related products are disclosed. The processing device includes a main unit and a plurality of basic units in communication with the...
2019/0065207 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM
A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and...
2019/0065206 Predictive Queue Control and Allocation
A predictive queue control and allocation system includes a queue and a queue control server communicatively coupled to the queue. The queue includes a first...
2019/0065205 VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD
A variable length instruction processor system and method is provided. Before a processor core executes an instruction, the system and method applied in a...
2019/0065204 MANAGED MULTIPLE DIE MEMORY QOS
Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A...
2019/0065203 INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION
A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a...
2019/0065202 POINTER-SIZE CONTROLLED INSTRUCTION PROCESSING
Instruction set architectures (ISAs) and apparatus and methods related thereto comprise a variable length instruction set that includes one or more...
2019/0065201 IMPLICIT GLOBAL POINTER RELATIVE ADDRESSING FOR GLOBAL MEMORY ACCESS
Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which...
2019/0065200 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS
Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a...
2019/0065199 SAVING AND RESTORING NON-CONTIGUOUS BLOCKS OF PRESERVED REGISTERS
Described herein are instruction set architectures (ISAs), and related data processing apparatuses and methods, with two or more non-contiguous blocks of...
2019/0065198 METHOD OF ALLOCATING A VIRTUAL REGISTER STACK IN A STACK MACHINE
Problem The problem to be solved is to seek an alternative to known instruction set architectures which provides the same or similar effects or is more ...
2019/0065197 PROVIDING EFFICIENT RECURSION HANDLING USING COMPRESSED RETURN ADDRESS STACKS (CRASs) IN PROCESSOR-BASED SYSTEMS
Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems is disclosed. In one aspect, a processor-based...
2019/0065196 REDUCED LOGIC LEVEL OPERATION FOLDING OF CONTEXT HISTORY IN A HISTORY REGISTER IN A PREDICTION SYSTEM FOR A...
Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction...
2019/0065195 INLINE DATA INSPECTION FOR WORKLOAD SIMPLIFICATION
A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a...
2019/0065194 APPARATUS AND METHODS FOR VECTOR OPERATIONS
Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a...
2019/0065193 APPARATUS AND METHODS FOR VECTOR OPERATIONS
Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a...
2019/0065192 APPARATUS AND METHODS FOR VECTOR OPERATIONS
Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a...
2019/0065191 Apparatus and Methods for Vector Based Transcendental Functions
Aspects for generating a dot product for two vectors in neural network are described herein. The aspects may include a controller unit configured to receive a...
2019/0065190 Apparatus and Methods for Matrix Multiplication
Aspects for matrix multiplication in neural network are described herein. The aspects may include a master computation module configured to receive a first...
2019/0065189 Apparatus and Methods for Comparing Vectors
Aspects for vector comparison in neural network are described herein. The aspects may include a direct memory access unit configured to receive a first vector...
2019/0065188 ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors...
2019/0065187 Apparatus and Methods for Vector Operations
Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a vector, wherein the...
2019/0065186 METHOD FOR MIN-MAX COMPUTATION IN ASSOCIATIVE MEMORY
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number...
2019/0065185 INSTRUCTION FOR DETERMINING HISTOGRAMS
A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry....
2019/0065184 APPARATUS AND METHODS FOR GENERATING DOT PRODUCT
Aspects for generating a dot product for two vectors in neural network are described herein. The aspects may include a controller unit configured to receive a...
2019/0065183 VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION
A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the...
2019/0065182 AUTOMATIC MACHINE-LEARNING HIGH VALUE GENERATOR
A processor-implemented method for generating a test suite within a time requirement is provided. The processor-implemented method includes executing a rule...
2019/0065181 AUTOMATIC MACHINE-LEARNING HIGH VALUE GENERATOR
A processor-implemented method for generating a test suite within a time requirement is provided. The processor-implemented method includes executing a rule...
2019/0065180 MODULAR POINTS-TO ANALYSIS
A method for analyzing code may include determining, using a dependency graph for the code, modules each including function definitions, and generating source...
2019/0065179 Software Feature Compilation with Runtime Configuration
A statement in a software code segment for an application that associates the software code segment to a feature is identified. The software code segment...
2019/0065178 INDICATOR REGRESSION AND MODELING FOR IMPLEMENTING SYSTEM CHANGES TO IMPROVE CONTROL EFFECTIVENESS
Embodiments of the present invention provide a system for indicator regression and modeling for implementing system changes to improve control effectiveness....
2019/0065177 CROSS APPLICATION BEHAVIOR CUSTOMIZATION
The example embodiments are directed to an application hub system and method configured to add a tenant-specific script to running instances of a plurality of...
2019/0065176 Method for Changing Over to a Firmware Version in an Electrical Control Unit for a Drive System, Electrical...
A method for changing over to a firmware version in an electrical control unit for a drive system, wherein the electrical control unit is suitable for...
2019/0065175 ELECTRONIC DEVICE
An electronic device includes a volatile memory; a non-volatile memory which is for storing firmware; and a circuit, wherein the firmware includes firmware...
2019/0065174 OVER-THE-AIR PROVISIONING OF APPLICATION LIBRARY
Techniques for updating an application installed on a communication device may include determining that an update for a private portion of the application is...
2019/0065173 MOBILE APPLICATION PROCESSING
Embodiments of the present application relate to a method, apparatus, and system for processing an app. The method includes obtaining a plugin identifier,...
2019/0065172 TECHNOLOGIES FOR CONFIGURATION-FREE PLATFORM FIRMWARE
Technologies for managing configuration-free platform firmware include a compute device, which further includes a management controller. The management...
2019/0065171 BINARY SUPPRESSION AND MODIFICATION FOR SOFTWARE UPGRADES
A remote security system may generate multiple different binary programs for corresponding operating system (OS) kernel versions that are to receive a software...
2019/0065170 DETACH VIRTUAL MACHINE FROM VIRTUAL MACHINE TEMPLATE
Mechanisms for detaching a thin-provisioned virtual machine (VM) from a VM template are disclosed. A request to detach a thin-provisioned VM from a VM template...
2019/0065169 ARCHITECTURES AND TECHNIQUES FOR RECORD PROTECTION AND FIELD MANAGEMENT
Architectures and Techniques for Record Protection and Field Management. A software package having one or more custom metadata types is installed. The software...
2019/0065168 APPARATUS AND METHOD TO SHORTEN SOFTWARE INSTALLATION TIME BASED ON A HISTORY OF FILE INSTALLATION
An apparatus acquires information identifying first-pieces of software that are candidates for installation, and estimates first files to be installed at a...
2019/0065167 SOFTWARE PACKAGE INSTALLATIONS WITH PROXIMITY TAGS
A method of installing a software package may include storing a software package coupon on a proximity tag coupled to a computing device; accessing the...
2019/0065165 AUTOMATED DEPLOYMENT OF APPLICATIONS
Functionality is disclosed for automated deployment of applications. A network-based deployment service provides functionality for deploying software...
2019/0065164 COMPUTER SPEED VIA METADATA-BASED BUSINESS RULE INTERPRETER
A method of increasing a speed of operation of a computer via a metadata-based business rule interpreter. The method includes receiving, at a processor, user...
2019/0065163 PARTIAL REDUNDANCY ELIMINATION WITH A FIXED NUMBER OF TEMPORARIES
A method for partial redundancy elimination with a fixed number of temporaries includes determining local data values of program code that describe a temporary...
2019/0065162 METHOD FOR INTRA-SUBGRAPH OPTIMIZATION IN TUPLE GRAPH PROGRAMS
A programming model generates a graph for a program, the graph including a plurality of nodes and edges, wherein each node of the graph represents an operation...
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