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Patent # Description
2019/0074289 SEMICONDUCTOR DEVICES INCLUDING INSULATING CAPPING STRUCTURES
A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically...
2019/0074288 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor device is described. A plurality of first films and a plurality of second films are alternately formed on a substrate....
2019/0074287 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the...
2019/0074286 METHOD OF REDUCING CHARGE LOSS IN NON-VOLATILE MEMORIES
An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first...
2019/0074285 FLASH MEMORY STRUCTURE WITH REDUCED DIMENSION OF GATE STRUCTURE
An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained...
2019/0074284 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a...
2019/0074283 MEMORY SYSTEM
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory...
2019/0074282 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral...
2019/0074281 METHODS OF FORMING PACKAGE STRUCTURES FOR ENHANCED MEMORY CAPACITY AND STRUCTURES FORMED THEREBY
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a...
2019/0074280 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the...
2019/0074279 METHOD FOR FABRICATING CONTACT PLUG IN DYNAMIC RANDOM ACCESS MEMORY
A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the...
2019/0074278 Semiconductor Device and Memory Device Including the Semiconductor Device
To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The...
2019/0074277 Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of...
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a...
2019/0074276 DISPLAY APPARATUS
A display apparatus that can reduce defects caused by static electricity, includes a substrate unit that includes at least one organic insulating layer, at...
2019/0074274 HIGH SURGE BI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR
A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions...
2019/0074273 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A source electrode can be patterned well in response to the densification of a semiconductor device. A first MOS transistor element is formed in a first...
2019/0074272 DUMMY CELL ARRANGEMENT AND METHOD OF ARRANGING DUMMY CELLS
A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region,...
2019/0074271 MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY
The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed...
2019/0074270 Self-assembly of Semiconductor Die onto a Leadframe Using Magnetic Fields
Integrated circuits may be assembled by placing a batch of integrated circuit (IC) die on a leadframe. Each of the IC die includes a magnetically responsive...
2019/0074269 ELECTRONIC COMPONENT
An electronic component is provided. The electronic component includes a substrate, an III-V die and a silicon die. The III-V die is disposed on the substrate....
2019/0074268 IMPROVED SYSTEM USING SYSTEM IN PACKAGE COMPONENTS
Methods, systems, and devices for enabling the use of SIP subsystems to make a configurable system with desired characteristics and features are provided. A...
2019/0074267 Semiconductor Device and Method of Forming a 3D Integrated System-in-Package Module
A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A...
2019/0074266 HIGH DENSITY PIXELATED-LED CHIPS AND CHIP ARRAY DEVICES
Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer...
2019/0074265 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first surface including a first region...
2019/0074264 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element...
2019/0074263 MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY
The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed...
2019/0074262 APPARATUS AND METHOD FOR MULTI-DIE INTERCONNECTION
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a...
2019/0074261 Integrated Fan-Out Package and the Methods of Manufacturing
A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad...
2019/0074260 INTERPOSER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
The disclosure provides an interposer substrate and a method for manufacturing the same. The method includes forming an insulating protection layer having a...
2019/0074259 CONDUCTIVE MICRO PIN
A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second...
2019/0074258 SOLDER PAD, SEMICONDUCTOR CHIP COMPRISING SOLDER PAD, AND FORMING METHOD THEREFOR
A solder pad, a semiconductor chip including the solder pad, and a forming method therefor are provided. A solder pad includes at least two metal layers and a...
2019/0074257 TECHNIQUE FOR DECOUPLING PLASMA ANTENNAE FROM ACTUAL CIRCUITRY
When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the...
2019/0074256 DEVICE HAVING PHYSICALLY UNCLONABLE FUNCTION, METHOD FOR MANUFACTURING SAME, AND CHIP USING SAME
The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for...
2019/0074255 POST-PASSIVATION INTERCONNECT STRUCTURE
A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying...
2019/0074254 METHOD OF ASSEMBLING QFP TYPE SEMICONDUCTOR DEVICE
A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding...
2019/0074253 ARC-RESISTANT CRACKSTOP
The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The...
2019/0074252 Electrical Devices and Methods for Forming Electrical Devices
An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation...
2019/0074251 SEMICONDUCTOR PACKAGES
Semiconductor packages are provided. A semiconductor package includes a package base substrate that includes a base layer. A plurality of connection terminals...
2019/0074250 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer...
2019/0074249 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked body that alternately includes a plurality of first films and a...
2019/0074248 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a...
2019/0074247 PRINTED CIRCUIT BOARD AND METHOD OF PACKAGING THE SAME
A printed circuit board contains: a first insulator including an upper surface, a lower surface, and a blind via passing through the first insulator; a first...
2019/0074246 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The...
2019/0074245 Component Carrier With Integrated Strain Gauge
A component carrier for carrying an electronic component on and/or in the component carrier, wherein the component carrier includes an interconnected stack...
2019/0074244 CIRCUIT ASSEMBLY AND METHOD FOR MANUFACTURING SAME
A circuit assembly that can be made small and a method for manufacturing the same are provided. A circuit assembly includes a substrate provided with a wiring...
2019/0074243 Transistor package with three-terminal clip
A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on...
2019/0074242 LEAD FRAME AND METHOD OF MANUFACTURING LEAD FRAME
A lead frame includes a plate portion provided with a first surface and a second surface, the second surface being opposite to the first surface; a protruding...
2019/0074241 LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING
The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls...
2019/0074240 INORGANIC WAFER HAVING THROUGH-HOLES ATTACHED TO SEMICONDUCTOR WAFER
A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic...
2019/0074239 HEAT TRANSFER ADAPTER PLATE
Example implementations relate to a heat transfer adapter plate. For example, a heat transfer adapter plate can comprise a first retention mechanism to couple...
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