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Patent # Description
2019/0074238 SEMICONDUCTOR DEVICE
Provided is a technique for improving product attachment. In a semiconductor device, the following expression is satisfied by an angle A formed by an imaginary...
2019/0074237 THERMOELECTRIC COOLER (TEC) FOR SPOT COOLING OF 2.5D/3D IC PACKAGES
While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated...
2019/0074236 POWER SEMICONDUCTOR DEVICE
In a power semiconductor device, the thickness dimension of a protective film of a semiconductor element is made smaller than that of an upper electrode, so a...
2019/0074235 DIAMOND-BASED HEAT SPREADING SUBSTRATES FOR INTEGRATED CIRCUIT DIES
The disclosed technology generally relates to integrated circuit (IC) packages, and more particularly to integrated circuit packages comprising perforated...
2019/0074234 METHOD FOR PRODUCING AIRTIGHT PACKAGE, AND AIRTIGHT PACKAGE
Provided is a method for producing an airtight package that can reduce thermal stress occurring in the inside of a glass lid due to irradiation with laser...
2019/0074233 HERMETICALLY SEALED MOLECULAR SPECTROSCOPY CELL WITH BURIED GROUND PLANE
A method for forming a sealed cavity includes bonding a non-conductive structure to a first substrate to form a non-conductive aperture into the first...
2019/0074232 TEST STRUCTURE AND MANUFACTURING METHOD THEREFOR
This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method...
2019/0074231 Stress Sensor for Semiconductor Components
An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of...
2019/0074230 TEMPLATE, TEMPLATE COMPONENT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a...
2019/0074229 METHODS FOR REDUCING CHIP TESTING TIME USING TRANS-THRESHOLD CORRELATIONS
A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC...
2019/0074228 METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An...
2019/0074227 Quick Adjustment Of Metrology Measurement Parameters According To Process Variation
Methods applicable in metrology modules and tools are provided, which enable adjusting metrology measurement parameters with respect to process variation,...
2019/0074226 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
The present application relates to the field of semiconductor technologies, and discloses a manufacturing method for a semiconductor device. The method may...
2019/0074225 Wrapped-Around Epitaxial Structure and Method
A method includes providing a device structure having a substrate, an isolation structure over the substrate, and two fins extending from the substrate and...
2019/0074224 INTEGRATED CIRCUIT STRUCTURE, GATE ALL-AROUND INTEGRATED CIRCUIT STRUCTURE AND METHODS OF FORMING SAME
The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate...
2019/0074223 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin...
2019/0074222 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of...
2019/0074221 HEIGHT DETECTING APPARATUS AND LASER PROCESSING APPARATUS
A spectral interference height detecting apparatus includes a chuck table for holding a workpiece thereon and a height detecting unit for detecting the height...
2019/0074220 THROUGH SUBSTRATE VIA (TSV) AND METHOD THEREFOR
A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of...
2019/0074219 Methods Of Producing Self-Aligned Vias
Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between...
2019/0074218 PROCESS OF FILLING THE HIGH ASPECT RATIO TRENCHES BY CO-FLOWING LIGANDS DURING THERMAL CVD
Methods for forming thin films in high aspect ratio feature definitions are provided. In one implementation, a method of processing a substrate in a process...
2019/0074217 CONDUCTIVE CONNECTORS HAVING A RUTHENIUM/ALUMINUM-CONTAINING LINER AND METHODS OF FABRICATING THE SAME
A conductive connector for a microelectronic structure may be formed in an opening in a dielectric layer, wherein a ruthenium/aluminum-containing liner is...
2019/0074216 Semiconductor Device
There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second...
2019/0074215 METHOD FOR DETERMINING A SUITABLE IMPLANTING ENERGY IN A DONOR SUBSTRATE AND PROCESS FOR FABRICATING A...
A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline...
2019/0074214 Method Of Manufacturing A Germanium-On-Insulator Substrate
A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to...
2019/0074213 METHOD FOR PRODUCING BONDED SOI WAFER
A method for producing a bonded SOI wafer, by ion implantation delamination to fabricate a bonded SOI wafer having a BOX layer and a SOI layer on a base wafer....
2019/0074212 Semiconductor Device and Semiconductor Wafer Including a Porous Layer and Method of Manufacturing
A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline...
2019/0074211 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having an active pattern extending in a first direction, a first gate structure and a second gate structure...
2019/0074210 MANUFACTURING METHOD OF ISOLATION STRUCTURE
A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor...
2019/0074209 DECHUCK CONTROL METHOD AND PLASMA PROCESSING APPARATUS
A dechuck control method of dechucking a processed object electrostatically attracted to an electrostatic chuck is provided. The method includes a step of...
2019/0074208 WAFER SUPPORTING SYSTEM
A wafer supporting system includes a supporting pedestal. The supporting pedestal includes a main supporting body and a hollow frame surrounding the supporting...
2019/0074207 Sectional Porous Carrier Forming a Temporary Impervious Support
Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive...
2019/0074206 TARGET SUBSTRATE WITH MICRO SEMICONDUCTOR STRUCTURES
A target substrate with micro semiconductor structures is manufactured by following steps of: attaching a pre-adhesive layer on a target substrate; patterning...
2019/0074205 SHIFTLESS WAFER BLADES
In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the...
2019/0074204 OVERHEAD TRANSPORT VEHICLE SYSTEM AND TEACHING METHOD FOR OVERHEAD TRANSPORT VEHICLE
Each overhead transport vehicle in an overhead transport vehicle system includes a winding drum to wind a hoisting material, attached to a lift stage to...
2019/0074203 SUBSTRATE CARRIER AND SUBSTRATE CARRIER STACK
A substrate carrier stack includes substrate carriers which are stacked or stackable on each other and carry substrates within an inner accommodation space of...
2019/0074202 STACK BOAT TOOL AND METHOD USING THE SAME
A stack boat tool includes a boat including a stack hole configured to accommodate first and second semiconductor packages; and a weight bar configured to be...
2019/0074200 SEMICONDUCTOR MANUFACTURING APPARATUS
According to an embodiment, a semiconductor manufacturing apparatus includes a holder configured to hold a processing object, a heater provided at the holder...
2019/0074199 ELECTRONIC DEVICE PACKAGE
Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic...
2019/0074198 METHODS FOR PRODUCING PACKAGED SEMICONDUCTOR DEVICES
A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier;...
2019/0074197 SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate...
2019/0074196 ELECTRONIC PACKAGE AND ITS PACKAGE SUBSTRATE
The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate...
2019/0074195 ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the...
2019/0074194 SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINUOUS PROFILE
Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least...
2019/0074193 METAL INTERCONNECT PROCESSING FOR AN INTEGRATED CIRCUIT METAL STACK
A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a...
2019/0074192 LASER ANNEALING APPARATUS AND SHEET RESISTANCE CALCULATION APPARATUS
A laser beam from a laser optical system is incident onto a semiconductor wafer. Thermal radiation light from the semiconductor wafer is incident onto an...
2019/0074191 ETCHING METHOD AND WORKPIECE PROCESSING METHOD
An etching method can protect a mask with a material having higher etching resistance to a silicon-containing film. The etching method is performed in a state...
2019/0074190 ETCHING METHOD
Provided is a method of etching a silicon-containing film made of at least one of silicon oxide and silicon nitride. The etching method includes: (i) preparing...
2019/0074189 METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS
Methods for manufacturing semiconductor devices may include forming a stack structure including layers stacked on a substrate, forming a mask pattern on the...
2019/0074188 COMPOSITIONS AND METHODS FOR ETCHING SILICON NITRIDE-CONTAINING SUBSTRATES
Described are compositions and methods useful for wet-etching a microelectronic device substrate that includes silicon nitride; the compositions including...
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