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Patent # Description
2019/0089392 Wireless Area Network Enabled Mobile Device Accessory
A wearable wireless portable device ("WWPD") includes cellular/WAN communications circuitry for establishing a direct connection to a telecommunication network...
2019/0089391 System, Apparatus And Method For Reducing Audio Artifacts In A Phase Diversity Receiver
In one embodiment, an apparatus includes: a first radio receiver to receive and downconvert a first radio frequency (RF) signal to a first digital signal; a...
2019/0089390 RECEIVING CIRCUIT AND WIRELESS COMMUNICATION DEVICE
A receiving circuit includes a first inductor, a second inductor, a capacitor and an amplifier. The first inductor includes a first terminal and a second...
2019/0089389 PREDISTORTION FOR TRANSMITTER WITH ARRAY
In certain aspects of the present disclosure, a method for wireless communication comprises predistorting a first signal based on a set of coefficients to...
2019/0089388 DIRECTIONAL DUAL-RADIO WIRELESS REPEATER
A wireless electronic device is provided. The wireless electronic device includes a first antenna and a first transceiver operatively coupled to the first...
2019/0089387 MULTIPLEXER, TRANSMISSION DEVICE, AND RECEPTION DEVICE
A multiplexer includes filters, a common terminal with which an inductance element is connected to a connection path of the common terminal and an antenna...
2019/0089386 METHOD AND TERMINAL DEVICE FOR EXECUTING RADIO APPLICATION
A method and a terminal device for executing a radio application are disclosed. The method for executing a radio application comprises the steps of: allowing a...
2019/0089385 RECONFIGURABLE FEC
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a...
2019/0089384 MEMORY SYSTEM
A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in...
2019/0089383 MEMORY SYSTEM
A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a...
2019/0089382 ERROR CORRECTION CIRCUIT, OPERATING METHOD THEREOF AND DATA STORAGE DEVICE INCLUDING THE SAME
An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being...
2019/0089381 GEL CODEWORD STRUCTURE ENCODING AND DECODING METHOD, APPARATUS, AND RELATED DEVICE
Disclosed is a GEL codeword structure encoding method. The method includes: first transforming an H.sub.C of a code B into an H.sup.B; obtaining a parity bit...
2019/0089380 POLAR CODE PROCESSING METHOD AND DEVICE
A method includes: dividing a first polar code into an odd number part and an even number part, where the odd number part of the first polar code includes bits...
2019/0089379 SYSTEMS AND METHODS FOR DECODING FORWARD ERROR CORRECTION CODES BASED ON COMPONENT CODES
Methods and apparatus for the decoding of forward error correction codes. One method includes decoding a number of component codes including code symbols, for...
2019/0089378 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD
The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data...
2019/0089377 MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system comprises an encoder that encodes by a graph code and a data holding unit that holds data to be used in encoding....
2019/0089376 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2019/0089375 CONVOLUTIONAL LDPC DECODING METHOD AND APPARATUS, DECODER, AND SYSTEM
The present disclosure provides a method, system, and terminal device for data transmission in an unlicensed spectrum, effectively reduce mutual signal...
2019/0089374 BIT FLIPPING ALGORITHM FOR PROVIDING SOFT INFORMATION DURING HARD DECISION HARD DECODING
A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of...
2019/0089373 MULTI-CHANNEL DECODER WITH DISTRIBUTED SCHEDULING
A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder...
2019/0089372 METHODS FOR DATA ENCODING IN DNA AND GENETICALLY MODIFIED ORGANISM AUTHENTICATION
A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message,...
2019/0089371 LOG COLLECTION DEVICE, LOG GENERATION DEVICE, AND LOG COLLECTION METHOD
There is provided a log collection device including: a log receiver that receives a text log from a log generation device; a dictionary generator that...
2019/0089370 PROGRAM COUNTER COMPRESSION METHOD AND HARDWARE CIRCUIT THEREOF
The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes...
2019/0089369 A/D CONVERTER
An A/D converter includes: an integrator circuit executing .DELTA..SIGMA. modulation to an analog signal to be converted; an adder outputting an addition...
2019/0089368 APPARATUS FOR REDUCING WANDERING SPURS IN A FRACTIONAL-N FREQUENCY SYNTHESIZER
The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital...
2019/0089367 PROGRAMMABLE GAIN AMPLIFIER AND A DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER CONTAINING THE PGA
A programmable gain amplifier includes an operational amplifier and a resistor network coupled to the output node of the operational amplifier. The resistor...
2019/0089366 ANALOG-TO-DIGITAL CONVERTER WITH NOISE ELIMINATION
An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital...
2019/0089365 AMPLIFIER CIRCUITRY, AD CONVERTER, AND WIRELESS COMMUNICATION DEVICE
Amplifier circuitry has sampling circuitry which samples an input voltage, a quantizer which quantizes an output voltage of the sampling circuitry and outputs...
2019/0089364 APPARATUS AND METHOD FOR GENERATING CLOCK SIGNAL WITH LOW JITTER AND CONSTANT FREQUENCY WHILE CONSUMING LOW POWER
A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a...
2019/0089363 FREQUENCY LOCKED LOOP WITH FAST VOLTAGE/FREQUENCY TRANSITION
The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency...
2019/0089362 CHARGE PUMP CIRCUIT AND PLL CIRCUIT
A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit...
2019/0089361 REFERENCELESS CLOCK AND DATA RECOVERY CIRCUITS
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate....
2019/0089360 Variable Delay
This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe...
2019/0089359 LOCK TIME MEASUREMENT OF CLOCK AND DATA RECOVERY CIRCUIT
A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter....
2019/0089358 Delay-Locked Loop (DLL) with Differential Delay Lines
An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a...
2019/0089357 APPARATUS AND METHOD FOR A PERMUTATION SEQUENCER
Aspects of the disclosure are directed to sequencing. In accordance with one aspect, sequencing includes creating a one hot list; selecting a current word of...
2019/0089356 Level Shifter Capable of Outputting Positive and Negative Voltages
The present application provides a level shifter comprising a first P-type transistor; a second P-type transistor; a third P-type transistor, coupled to the...
2019/0089355 SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates...
2019/0089354 Low Power Clock Gating Circuit
A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry...
2019/0089353 INPUT ELEMENT AND INPUT DEVICE
An input element includes: a first electrode and a second electrode that face each other; and an intermediate layer disposed between the first and the second...
2019/0089352 PROXIMITY SENSOR CONNECTION MECHANISM
An electronic device includes: a display assembly including an electronic display configured to generate an optical image viewable from in front of the...
2019/0089351 POWER MODULE
A communication signal terminal receives a first communication signal which includes an address of a first IC and a first configuration value for the first IC,...
2019/0089350 METHOD AND SYSTEM FOR CONTROLLING VOLTAGE BALANCE OF A SERIALIZED POWER SWITCHING DEVICE
The present disclosure relates to a method for controlling voltage balance of a serialized power switching device, comprising generating a reference voltage...
2019/0089349 SWITCHING CIRCUIT
A switching circuit may include a first switching element, a second switching element, a high potential wiring, a low potential wiring, a gate wiring...
2019/0089347 DRIVE CIRCUIT
A drive circuit includes a first level shift circuit, a second level shift circuit, a pre-driver, and a high-side transistor. The first level shift circuit...
2019/0089346 CONTROL CIRCUIT, CONTROL METHOD, AND NON-TRANSITORY STORAGE MEDIUM
A control circuit, which is one aspect of the present invention, controls a gate signal input to a semiconductor switching element. The control circuit...
2019/0089345 DEVICE AND METHOD FOR GENERATING A DIFFERENTIAL VOLTAGE
A circuit and a method are described for generating differential voltages.
2019/0089344 PROTECTION CIRCUIT, OSCILLATION COMPENSATION CIRCUIT AND POWER SUPPLY CIRCUIT IN SOLID STATE PULSE MODULATOR
The disclosed technology relates to a gate protection circuit for an Insulated Gate Bipolar Transistor (IGBT), the IGBT being used as a switch device in a...
2019/0089343 MOS POWER TRANSISTORS IN PARALLEL CHANNEL CONFIGURATION
A circuit comprises a first metal-oxide semiconductor, MOS, power transistor having a first gate terminal, a first drain terminal, and a first source terminal,...
2019/0089342 A circuit and a method for driving electrical loads
A circuit and a corresponding method for driving one or more electric loads are described, comprising: a generator (110) of an electric current waveform, and a...
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