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Patent # Description
2019/0088785 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such...
2019/0088784 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, BASE SUBSTRATE AND DISPLAY DEVICE
A thin film transistor, and a method for manufacturing the thin film transistor, a base substrate and a display device are provided. The method includes:...
2019/0088783 METHOD FOR MANUFACTURING COMPACT OTP/MTP TECHNOLOGY
Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate...
2019/0088782 METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE
The present invention provides a method for fabricating a semiconductor structure, the method at least comprises: firstly, a substrate is provided, a...
2019/0088781 Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink-Harmonic...
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and...
2019/0088780 DEMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A DEMOS transistor includes a semiconductor substrate defining a field region and an active region, a gate pattern disposed on the semiconductor substrate, the...
2019/0088779 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an...
2019/0088778 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane; a first and a second electrode;...
2019/0088777 COMPOSITE ETCH STOP LAYER FOR CONTACT FIELD PLATE ETCHING
The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source...
2019/0088776 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device comprising a drain layer, a base region, a source region, a field plate electrode, and a gate region. The...
2019/0088775 SEMICONDUCTOR DEVICE
According to an embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a third semiconductor...
2019/0088774 SEMICONDUCTOR DEVICE
According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a plurality of second...
2019/0088773 REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer;...
2019/0088772 BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY
A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate...
2019/0088771 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a...
2019/0088770 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third...
2019/0088769 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes a semiconductor layer having a first and a second plane; emitter and collector electrode; a trench...
2019/0088768 BIPOLAR TRANSISTOR AND RADIO-FREQUENCY POWER AMPLIFIER MODULE
A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The...
2019/0088767 METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED GATES AND GATE EXTENSIONS AND THE...
Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In...
2019/0088766 METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN SOURCE/DRAIN REGIONS OF A TRANSISTOR DEVICE FORMED ON AN SOI...
One illustrative method disclosed herein includes, among other things, forming a sacrificial sidewall spacer adjacent a sidewall spacer of a transistor and,...
2019/0088765 COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded...
2019/0088764 SELF-ALIGNED CONTACTS FOR VERTICAL FIELD EFFECT TRANSISTOR CELL HEIGHT SCALING
A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from...
2019/0088763 SEMICONDUCTOR DEVICE GATE STRUCTURE AND METHOD OF FABRICATING THEREOF
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer...
2019/0088762 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a...
2019/0088761 SAWTOOH ELECTRIC FIELD DRIFT REGION STRUCTURE FOR PLANAR AND TRENCH POWER SEMICONDUCTOR DEVICES
A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+...
2019/0088759 TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE
Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate...
2019/0088758 THIN FILM TRANSISTOR INCLUDING HIGH-DIELECTRIC INSULATING THIN FILM AND METHOD OF FABRICATING THE SAME
Disclosed are a thin film transistor including a substrate and a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain...
2019/0088757 ONE-DIMENSIONAL NANOSTRUCTURE GROWTH ON GRAPHENE AND DEVICES THEREOF
A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of...
2019/0088756 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin...
2019/0088755 VERTICAL TRANSISTORS HAVING MULTIPLE GATE THICKNESSES
Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a...
2019/0088754 VERTICAL TRANSISTORS HAVING MULTIPLE GATE THICKNESSES
Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a...
2019/0088753 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second...
2019/0088752 THIN FILM TRANSISTOR SUBSTRATE
A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and...
2019/0088751 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY DEVICE
The disclosure discloses a thin film transistor and a manufacturing method therefor, an array substrate, and a displaying device. The TFT includes a first...
2019/0088750 SEMICONDUCTOR DEVICE
A semiconductor device includes a drain layer, a drift layer, a base region, a source region, trenches, base contact region, gate regions, and field plate...
2019/0088749 SEMICONDUCTOR DEVICE AND CONTROL SYSTEM
According to an embodiment, a semiconductor device includes a first semiconductor layer, a first switching element, a second switching element, and a...
2019/0088748 NANOPOROUS SEMICONDUCTOR MATERIALS AND MANUFACTURE THEREOF
Methods for forming nanoporous semiconductor materials are described. The methods allow for the formation of micron-scale arrays of sub-10nm nanopores in...
2019/0088747 SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES
A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V...
2019/0088746 SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL
A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum...
2019/0088745 REVERSE CONDUCTING IGBT INCORPORATING EPITAXIAL LAYER FIELD STOP ZONE
An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial...
2019/0088744 SEMICONDUCTOR SUBSTRATE STRUCTURES AND SEMICONDUCTOR DEVICES
A semiconductor substrate structure includes a semiconductor substrate having a first conductivity type, and a first buried well region disposed in the...
2019/0088743 MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first...
2019/0088742 SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN CONTACTS AND A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION
A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer...
2019/0088741 High Efficiency Room Temperature Infrared Sensor
An infrared (IR) detection sensor for detecting IR radiation. The IR detection sensor including a plurality of nanowires positioned adjacent to each other so...
2019/0088740 SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES
The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in...
2019/0088739 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an...
2019/0088738 SEMICONDUCTOR DEVICE
A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity...
2019/0088737 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes a semiconductor layer having first and second planes; first and second electrodes; a first...
2019/0088736 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral ...
2019/0088735 Vertical Semiconductor Structure
A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first...
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