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Patent # Description
2019/0088684 THIN FILM TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A thin film transistor structure is provided with a glass substrate, a buffer layer, a metal oxide semiconductor layer, a gate insulating layer, a gate metal...
2019/0088683 ARRAY SUBSTRATE, DISPLAY PANEL AND PIXEL PATCHING METHOD
The present application provides an array substrate, which comprises a plurality of gate lines, a plurality of data lines, a plurality of thin film...
2019/0088681 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
An array substrate, a method for manufacturing the array substrate, and a display device are provided. The array substrate includes a base, and a common...
2019/0088680 STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM
A semiconductor device includes at least two stacked SOI levels or configurations, each of which may include transistor elements formed on the basis of a given...
2019/0088679 POWER GATE SWITCHING SYSTEM
A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line...
2019/0088678 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on...
2019/0088677 THREE-DIMENSIONAL STRUCTURED MEMORY DEVICES
A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain...
2019/0088676 SEMICONDUCTOR MEMORY
According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of...
2019/0088675 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film....
2019/0088674 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first electrode layer having a first area, a second area, and a connection area...
2019/0088673 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the...
2019/0088672 MULTI-LAYER WIRING STRUCTURE, METHOD FOR MANUFACTURING MULTI-LAYER WIRING STRUCTURE, AND SEMICONDUCTOR DEVICE
According to one embodiment, a multi-layer wiring structure includes a first multi-layer section, first contact plugs, and pillars. First conductors and first...
2019/0088671 Methods Used In Forming An Array Of Elevationally-Extending Transistors
A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space....
2019/0088670 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the...
2019/0088669 OXIDE FORMATION IN A PLASMA PROCESS
A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma...
2019/0088668 NOR Memory Cell with Vertical Floating Gate
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from...
2019/0088667 NOR Memory Cell with L-Shaped Floating Gate
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a second substrate region...
2019/0088666 Structure and Method for Single Gate Non-Volatile Memory Device
The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of...
2019/0088665 COMPACT EEPROM MEMORY CELL
An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state...
2019/0088664 MEMORY DEVICE
A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first...
2019/0088663 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected...
2019/0088662 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a...
2019/0088661 CONDUCTIVE LAYERS WITH DIFFERENT THICKNESSES
A semiconductor chip includes: a memory cell having a bit line, a word line, and a power supply node; a first conductive line formed in a first conductive...
2019/0088660 BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS THAT FACILITATE DIRECT WRITING FOR STORAGE
Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell...
2019/0088659 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other,...
2019/0088658 SEMICONDUCTOR DEVICES
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas...
2019/0088657 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a...
2019/0088656 DATA STORAGE DEVICES AND METHODS OF MANUFACTURING THE SAME
Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a...
2019/0088655 MEMORY ELEMENT
According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer...
2019/0088654 CIRCUIT AND LAYOUT FOR SINGLE GATE TYPE PRECHARGE CIRCUIT FOR DATA LINES IN MEMORY DEVICE
Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion...
2019/0088653 Memory Cells and Memory Arrays
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced...
2019/0088652 Memory Cells and Memory Arrays
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors....
2019/0088651 MEMORIES AND METHODS TO PROVIDE CONFIGURATION INFORMATION TO CONTROLLERS
A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a...
2019/0088650 Cut Metal Gate with Slanted Sidewalls
A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first...
2019/0088649 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation...
2019/0088648 SEMICONDUCTOR DEVICE
A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a...
2019/0088647 ANTI-FUSE FOR USE IN SEMICONDUCTOR DEVICE
An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate...
2019/0088646 E-FUSE FOR USE IN SEMICONDUCTOR DEVICE
An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other;...
2019/0088645 Double-Base-Connected Bipolar Transistors with Passive Components Preventing Accidental Turn-On
The present application discloses new approaches to providing "passive-off" protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC...
2019/0088644 VERTICAL NOISE REDUCTION IN 3D STACKED SEMICONDUCTOR DEVICES
A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may...
2019/0088643 THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The...
2019/0088642 RF Amplifier Package with Biasing Strip
Embodiments of an RF amplifier package include a body section comprising an upper surface having first and second opposing edge sides, and a die pad vertically...
2019/0088641 BI-DIRECTIONAL SNAPBACK ESD PROTECTION CIRCUIT
An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node...
2019/0088640 SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device...
2019/0088639 INTEGRATED CIRCUITS WITH STANDARD CELL
The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and...
2019/0088638 INTEGRATED CIRCUITS WITH STANDARD CELL
The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second...
2019/0088637 Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an...
A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the...
2019/0088636 LAMINATED INTERPOSERS AND PACKAGES WITH EMBEDDED TRACE INTERCONNECTS
Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical...
2019/0088635 Semiconductor Package, Semiconductor Device and Method of Forming the Same
According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component...
2019/0088634 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory...
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