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Patent # Description
2019/0088582 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a...
2019/0088581 Packages with Si-Substrate-Free Interposer and Method Forming Same
A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked...
2019/0088580 MULTI-ROW WIRING MEMBER FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating...
2019/0088579 METHODS OF FORMING LEADLESS SEMICONDUCTOR PACKAGES WITH PLATED LEADFRAMES AND WETTABLE FLANKS
A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate...
2019/0088578 SUBSTRATE FOR SEMICONDUCTOR ELEMENTS AND SEMICONDUCTOR DEVICE
A substrate for semiconductor elements includes a terminal part including a first surface, a second surface opposite to the first surface, and side surfaces...
2019/0088577 SEMICONDUCTOR DEVICE
Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and...
2019/0088576 PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR
A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC...
2019/0088575 SEMICONDUCTOR MODULE
A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the...
2019/0088574 PACKAGED ELECTRONIC DEVICE HAVING STEPPED CONDUCTIVE STRUCTURE AND RELATED METHODS
An electronic package includes a substrate having a conductive element. The conductive element includes a stepped portion disposed at an end of the conductive...
2019/0088573 ADHESIVE FOR SEMICONDUCTOR MOUNTING, AND SEMICONDUCTOR SENSOR
Provided is an adhesive for semiconductor mounting that can achieve high-precision gap control and can increase heat resistance when a semiconductor is...
2019/0088572 HEAST SINK FASTENING SEAT FOR USE WITH ELECTRICAL CONNECTOR
An electrical connector assembly includes an electrical connector mounted upon a printed circuit board, and a heat sink fastening seat mounted upon the printed...
2019/0088571 DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO LEADFRAME ATTACH
A packaged power transistor device includes a Direct-Bonded Copper ("DBC") substrate. Contact pads of a first lead are attached with solderless welds to a...
2019/0088570 SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
The present disclosure relates to a semiconductor device, a solid-state imaging device, and an electronic apparatus that can reduce warping. In a mounted...
2019/0088569 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface...
2019/0088568 SEMICONDUCTOR DEVICE
In a semiconductor device, a plurality of semiconductor chips included in an upper-arm circuit are connected in parallel between a pair of upper-arm plates,...
2019/0088567 Inorganic Packaging Module Having a Chip Encapsulated Therein
A packaging module includes a substrate, a chip firmly mounted on the substrate, a frame firmly connected to the substrate via a gold-to-gold bonding and a...
2019/0088566 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a core member having a through-hole. A semiconductor chip is in the through-hole and has an active surface with...
2019/0088565 Face Down Dual Sided Chip Scale Memory Package
A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active...
2019/0088564 PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a...
2019/0088563 Semiconductor Device with Copper Corrosion Inhibitors
A semiconductor device includes a semiconductor substrate and a metal structure in electrical contact with the semiconductor substrate. The metal structure has...
2019/0088562 ELECTRONIC DEVICE COMPRISING A SUPPORT SUBSTRATE AND AN ENCAPSULATING COVER FOR AN ELECTRONIC COMPONENT
A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An...
2019/0088561 CELL-LIKE FLOATING-GATE TEST STRUCTURE
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout,...
2019/0088560 MULTI-PLATE SEMICONDUCTOR WAFER TESTING SYSTEMS
In some embodiments, a semiconductor wafer testing system comprises a first plate configured to couple to a probe head, the first plate including a first...
2019/0088559 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device of the present invention includes at least following four steps. (A) A step of preparing a structure having...
2019/0088558 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation...
2019/0088557 INTEGRATED CIRCUIT STRUCTURE INCLUDING DEEP N-WELL SELF-ALIGNED WITH STI AND METHOD OF FORMING SAME
The disclosure is directed to integrated circuit (IC) structures, and more particularly, to IC structures including a deep n-well that is self-aligned with a...
2019/0088556 HIGH-K METAL GATE AND METHOD FOR FABRICATING THE SAME
Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer...
2019/0088555 METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over...
2019/0088554 Electronic Device Including a Drift Region
An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the...
2019/0088553 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial...
2019/0088552 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially...
2019/0088551 SEMICONDUCTOR DEVICES HAVING FIN-SHAPED ACTIVE REGIONS
Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The...
2019/0088550 Composite Wafer, Semiconductor Device, Electronic Component and Method of Manufacturing a Semiconductor Device
In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being...
2019/0088549 WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the...
2019/0088548 SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing apparatus has a groove former configured to form a groove on one surface of a semiconductor wafer, on which a plurality of...
2019/0088547 INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME
An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die...
2019/0088546 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive...
2019/0088545 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
In a manufacturing method of a semiconductor device according to the present embodiment, a semiconductor substrate, which has a first face and a second face,...
2019/0088544 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A method for forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in a first surface of a...
2019/0088543 SELECTIVELY ETCHED SELF-ALIGNED VIA PROCESSES
Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a...
2019/0088542 Contact Structure for Semiconductor Device
A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the...
2019/0088541 FULLY ALIGNED VIA IN GROUND RULE REGION
The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure...
2019/0088540 METHODS AND APPARATUS FOR FILLING SUBSTRATE FEATURES WITH COBALT
Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a...
2019/0088539 METHOD FOR FORMING METAL WIRING
A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by...
2019/0088538 DIFFUSION BARRIERS
In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of...
2019/0088537 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is...
2019/0088536 CONTROL METHOD FOR DIFFERENTIATED ETCHING DEPTH
A control method for differentiated etching depth is provided. The method includes: providing a first etching stop pattern layer in a panel having stacked...
2019/0088535 METHOD FOR FORMING LEAD WIRES IN HYBRID-BONDED SEMICONDUCTOR DEVICES
Embodiments of hybrid-bonded semiconductor structures and methods for forming a hybrid-bonded semiconductor structure are disclosed. The method can include...
2019/0088534 Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid...
2019/0088533 METHOD FOR FABRICATING PLANARIZATION LAYER
A method for fabricating a planarization layer includes: forming an active device on a substrate; covering the active device with a passivation layer; forming...
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