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Patent # Description
2019/0087366 APPARATUSES AND METHODS FOR ASYMMETRIC INPUT/OUTPUT INTERFACE FOR A MEMORY
Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The...
2019/0087365 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in...
2019/0087364 INTEGRATED CIRCUIT MEMORY DEVICES WITH CUSTOMIZABLE STANDARD CELL LOGIC
Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type...
2019/0087363 MULTILEVEL MEMORY BUS SYSTEM
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state...
2019/0087362 STORAGE DEVICE COMMUNICATING WITH HOST ACCORDING TO MULTICAST COMMUNICATION PROTOCOL AND COMMUNICATION METHOD...
A storage device includes a memory device; and a controller configured to fetch a command from a host, the command indicating a logical address, process the...
2019/0087361 SEMICONDUCTOR INTEGRATED CIRCUIT
According to one embodiment, a semiconductor integrated circuit includes a bus master, a bus slave and a clock gating circuit. The bus master outputs an access...
2019/0087360 SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a...
2019/0087359 SYSTEM AND METHOD FOR SECURELY CONNECTING TO A PERIPHERAL DEVICE
A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and...
2019/0087358 SUPPORT INFORMATION PROVISIONING SYSTEM
A support information provisioning system a support device, an external device; and a customer device. The customer device includes an external connector and a...
2019/0087357 POWER CONVERSION SYSTEM AND CONTROLLING METHOD THEREOF
A power conversion system is disclosed, which comprises at least one conversion unit comprising a converter unit and a first power interface boards; at least...
2019/0087356 SYSTEM AND METHODS FOR MIXED -SIGNAL COMPUTING
Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals...
2019/0087355 MEMORY ACCESS CONTROL USING ADDRESS ALIASING
The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of...
2019/0087354 System, Apparatus And Method For Integrity Protecting Tenant Workloads In A Multi-Tenant Computing Environment
In one embodiment, an apparatus includes a core to execute instructions, where in response to a first instruction, the core is to obtain an encrypted binary of...
2019/0087353 DATA STORAGE APPARATUS
According to one embodiment, a data storage apparatus includes a processor. The processor protects data on a memory by encryption in a first mode or a second...
2019/0087352 METHOD AND SYSTEM TRANSMITTING DATA BETWEEN STORAGE DEVICES OVER PEER-TO-PEER (P2P) CONNECTIONS OF PCI-EXPRESS
Provided are a method and a system for transmitting data between storage devices over peer-to-peer (P2P) connections of peripheral component ...
2019/0087351 TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT
According to various aspects, a memory management unit (MMU) having multiple parallel translation machines may collect transactions in an incoming transaction...
2019/0087350 INTELLIGENTLY PARTITIONING DATA CACHE TO ALLOCATE SPACE FOR TRANSLATION ENTRIES
A processor architecture which partitions the on-chip data caches to efficiently cache translation entries alongside data which reduces the conflicts between...
2019/0087349 DATA STORAGE DEVICE AND DATA STORAGE METHOD
The data storage method includes selecting one of a plurality of blocks in a flash memory as an active block; dividing the active block into a plurality of...
2019/0087348 DATA BACKUP METHOD, DATA RECOVERY METHOD AND STORAGE CONTROLLER
A data backup method is provided. The data backup method includes maintaining a logical-to-physical table (L2P table) in a memory, where the L2P table records...
2019/0087347 INITIALIZING A DATA STRUCTURE FOR USE IN PREDICTING TABLE OF CONTENTS POINTER VALUES
Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module,...
2019/0087346 INITIALIZING A DATA STRUCTURE FOR USE IN PREDICTING TABLE OF CONTENTS POINTER VALUES
Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module,...
2019/0087345 Performance By Retaining High Locality Data In Higher Level Cache Memory
Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include...
2019/0087344 Reducing Clean Evictions In An Exclusive Cache Memory Hierarchy
Various aspects include methods for implementing reducing clean evictions in an exclusive cache memory hierarchy on a computing device. Various aspects may...
2019/0087343 Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same
The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the...
2019/0087342 DYNAMIC PREMIGRATION THROTTLING FOR TIERED STORAGE
A dynamic premigration protocol is implemented in response to a secondary tier returning to an operational state and an amount of data associated with a...
2019/0087341 METHOD AND SYSTEM FOR COORDINATING BASELINE AND SECONDARY PREFETCHERS
In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to...
2019/0087340 CACHE MANAGEMENT IN A STREAM COMPUTING ENVIRONMENT THAT USES A SET OF MANY-CORE HARDWARE PROCESSORS
Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples...
2019/0087339 CACHE SYNONYM SYSTEM AND METHOD
A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with...
2019/0087338 CACHE SYNONYM SYSTEM AND METHOD
A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with...
2019/0087337 TABLE OF CONTENTS CACHE ENTRY HAVING A POINTER FOR A RANGE OF ADDRESSES
Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a...
2019/0087336 SET TABLE OF CONTENTS (TOC) REGISTER INSTRUCTION
A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a...
2019/0087335 TABLE OF CONTENTS CACHE ENTRY HAVING A POINTER FOR A RANGE OF ADDRESSES
Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a...
2019/0087334 SET TABLE OF CONTENTS (TOC) REGISTER INSTRUCTION
A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a...
2019/0087333 CONVERTING A STALE CACHE MEMORY UNIQUE REQUEST TO A READ UNIQUE SNOOP RESPONSE IN A MULTIPLE (MULTI-) CENTRAL...
Converting a stale cache memory unique request to a read unique snoop response in a multiple (multi-) central processing unit (CPU) processor is disclosed. The...
2019/0087332 OPERATION METHOD OF MEMORY CONTROLLER AND OPERATION METHOD OF STORAGE DEVICE INCLUDING THE SAME
An operation method of a memory controller which is configured to control a nonvolatile memory device includes receiving a command from the outside,...
2019/0087331 DEBUG DATA RECOVERY AFTER PLI EVENT
The present disclosure generally relates to a storage device sensing critical failure or PLI events and writing the debug data to a memory device so that when...
2019/0087330 NONVOLATILE STORAGE USING LOW LATENCY AND HIGH LATENCY MEMORY
Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of...
2019/0087329 SEMICONDUCTOR DEVICE AND PROGRAM USED IN THE SEMICONDUCTOR DEVICE
The present disclosure provides a technique of suppressing competition of processes in a semiconductor device employing a multilayer bus configuration. A...
2019/0087328 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory....
2019/0087327 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory....
2019/0087326 Data Storage Device and Operating Method Thereof
A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host...
2019/0087325 MEMORY SYSTEM
According to one embodiment, a memory system, comprises a non-volatile memory; a first memory and a second memory; and a memory controller configured to...
2019/0087324 MEMORY SYSTEM AND METHOD
According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive...
2019/0087323 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first...
2019/0087322 HARDWARE-BASED FLASH FTL FUNCTION REALIZATION METHOD AND DATA STORAGE DEVICE THEREOF
Disclosed in an embodiment of the present invention are a hardware-based flash FTL function realization method and data storage device thereof, wherein the...
2019/0087321 Re-playable Execution Optimized for Page Sharing in a Managed Runtime Environment
Embodiments of this disclosure allow non-position-independent-code to be shared between a closed application and a subsequent application without converting...
2019/0087320 GARBAGE COLLECTION FOR DATA STORAGE
Methods, systems, apparatus, including computer programs encoded on computer storage media, for reclaiming storage space in a storage environment. In one...
2019/0087318 SYSTEM AND METHOD FOR TRANSFERRING CONTROL OF INSTRUCTION EXECUTION BETWEEN ADDRESS SPACES
Disclosed are system and method for controlling execution of a computer program. An example method includes determining whether code instructions or data of...
2019/0087317 PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
Processing prefetch memory operations and transactions. A local processor receives a prefetch request from a remote processor. Prior to execution of the...
2019/0087316 DYNAMICALLY ALLOCATED THREAD-LOCAL STORAGE
Dynamically allocated thread storage in a computing device is disclosed. The dynamically allocated thread storage is configured to work with a process...
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