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Patent # Description
2019/0097656 MIN-SUM DECODING FOR LDPC CODES
Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a...
2019/0097655 LOW-DENSITY PARITY-CHECK CODE DECODER AND DECODING METHOD
A low-density parity-check (LDPC) code decoding method for decoding a set of initial log likelihood ratio (LLR) outputted by a de-mapping circuit. The decoding...
2019/0097654 MEMORY SYSTEM WITH ON-THE-FLY ERROR DETECTION AND TERMINATION AND OPERATING METHOD THEREOF
Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for...
2019/0097653 MEMORY SYSTEM WITH DECODERS AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND DECODERS
A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods...
2019/0097652 MEMORY SYSTEM DECODING DESIGN AND OPERATING METHOD THEREOF
A semiconductor memory system and an operating method thereof include a plurality of memory devices; and a controller coupled with the memory devices and...
2019/0097651 TIMING FOR IC CHIP
A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware...
2019/0097650 ENCODERS, DECODERS, AND METHODS
An encoder for encoding input data to generate corresponding encoded data is provided. The encoder (10) is operable to process a sequence of elements in the...
2019/0097649 ENTROPY ENCODING AND DECODING SCHEME
Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective...
2019/0097648 SAR-TYPE ANALOG-DIGITAL CONVERTER USING RESIDUE INTEGRATION
The present invention relates to a successive approximation register (SAR)-type analog-digital converter (ADC), which can amplify a residual voltage without a...
2019/0097647 Delta sigma modulator
A .DELTA..SIGMA. modulator includes a first integrator which has first and second capacitors and integrates an analog input signal and a feedback analog...
2019/0097646 Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods
An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the...
2019/0097645 ANALOG TO DIGITAL CONVERSION APPARATUS AND ANALOG TO DIGITAL CONVERTER CALIBRATION METHOD OF THE SAME
An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is...
2019/0097644 CURRENT SOURCE NOISE CANCELLATION
At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second...
2019/0097643 ATOMIC OSCILLATOR AND FREQUENCY SIGNAL GENERATION SYSTEM
An atomic oscillator includes a semiconductor laser housed in a container, an atom cell housing alkali metal atoms and irradiated with a light output from the...
2019/0097642 CLOCK GENERATION CIRCUIT AND CLOCK SIGNAL GENERATION METHOD
A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source...
2019/0097641 CALIBRATION OF A VOLTAGE CONTROLLED OSCILLATOR TO TRIM THE GAIN THEREOF, USING A PHASE LOCKED LOOP AND A...
Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase...
2019/0097640 PHASE-LOCKED LOOP OUTPUT ADJUSTMENT
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference...
2019/0097639 FAST LOCKING CLOCK AND DATA RECOVERY CIRCUIT
A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an...
2019/0097638 JITTER REDUCTION IN CLOCK AND DATA RECOVERY CIRCUITS
Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to...
2019/0097637 CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS
Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices...
2019/0097636 DYNAMIC MULTICYCLES FOR CORE-PERIPHERY TIMING CLOSURE
Methods and systems for timing analysis and closure during logic synthesis of synchronous digital circuitry are provided, which may be used to prevent timing...
2019/0097635 Techniques For Reducing Uneven Aging In Integrated Circuits
An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the...
2019/0097634 SYNCHRONIZING A SELF-TIMED PROCESSOR WITH AN EXTERNAL EVENT
There is disclosed a self-timed processor. The self-timed processor includes trigger logic having a trigger input to receive an event trigger signal, a data...
2019/0097633 HIGH-VOLTAGE LEVEL-SHIFTER CIRCUITRY
High-voltage level-shifter architectures that provide galvanic coupling between low/high-voltage domains while simultaneously enabling high speed operation,...
2019/0097632 CURRENT-MODE PUF CIRCUIT BASED ON REFERENCE CURRENT SOURCE
A current-mode PUF circuit based on a reference current source comprises an input register, the reference current source, a deviation current comparator and a...
2019/0097631 LOW LEAKAGE POWER SWITCH
Computer systems may include multiple power switch circuits for coupling circuit blocks to power supply signals. Different power supply signals may be selected...
2019/0097630 DYNAMIC TERMINATION EDGE CONTROL
Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode...
2019/0097629 Sensor Unit
To provide a sensor unit that simultaneously displays other information together with a threshold and a physical quantity. A sensor unit causes a dot-matrix...
2019/0097628 SAFE SWITCHING DEVICE
Method and device for safe switching of a signal between a first and second point. Device includes a first branch having a first switch and second switch...
2019/0097627 Independent Control of Branch FETs for RF Performance Improvement
A FET-based RF switch architecture and method that provides for independent control of FETs within component branches of a switching circuit. With independent...
2019/0097626 REDUCED-POWER ELECTRONIC CIRCUITS WITH WIDE-BAND ENERGY RECOVERY USING NON-INTERFERING TOPOLOGIES
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a...
2019/0097625 Radio Frequency Switching Circuit with Distributed Switches
An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the...
2019/0097624 Circuit Based on a III/V Semiconductor and a Method of Operating the Same
An electronic circuit provided with a III/V semiconductor domain, and a method of operating such a circuit is presented. In particular, the present application...
2019/0097623 LOW POWER CONSUMPTION POWER-ON RESET CIRCUIT AND REFERENCE SIGNAL CIRCUIT
A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator...
2019/0097622 LOW LEAKAGE POWER SWITCH
A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power...
2019/0097620 DYNAMIC CONTROL OF EDGE SHIFT FOR DUTY CYCLE CORRECTION
A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The...
2019/0097619 STATIC COMPENSATION OF AN ACTIVE CLOCK EDGE SHIFT FOR A DUTY CYCLE CORRECTION CIRCUIT
Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device...
2019/0097618 CORRECTING DUTY CYCLE AND COMPENSATING FOR ACTIVE CLOCK EDGE SHIFT
The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system...
2019/0097617 CORRECTING DUTY CYCLE AND COMPENSATING FOR ACTIVE CLOCK EDGE SHIFT
The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system...
2019/0097616 STATIC COMPENSATION OF AN ACTIVE CLOCK EDGE SHIFT FOR A DUTY CYCLE CORRECTION CIRCUIT
Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device...
2019/0097615 INPUT/OUTPUT CIRCUIT
A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power...
2019/0097614 Level Shifter, and Source Driver, Gate Driver and Display Device Including the Same
A level shifter includes (a) an input unit including (i) a first input transistor configured to receive a first voltage and connected to a first connection...
2019/0097613 METHODS AND APPARATUSES OF A TWO-PHASE FLIP-FLOP WITH SYMMETRICAL RISE AND FALL TIMES
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator...
2019/0097612 Low Noise Charge Pump Method and Apparatus
A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both...
2019/0097611 REDUCED-POWER ELECTRONIC CIRCUITS WITH WIDE-BAND ENERGY RECOVERY USING NON-INTERFERING TOPOLOGIES
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network...
2019/0097610 TRANSMITTERS-BASED LOCALIZATION AT INTERSECTIONS IN URBAN ENVIRONMENTS
New measurement inputs for Kalman Filter or similar estimation approaches (at each sample) may include: DSRC messages from roadside transmitters (RSTs), such...
2019/0097609 Five-Level Switched-Capacitance DAC Using Bootstrapped Switches
A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The...
2019/0097608 MULTI-BAND FILTER ARCHITECTURES
Certain aspects of the present disclosure relate to multi-band filter architectures and methods for filtering signals using the multi-band filter...
2019/0097607 ELASTIC WAVE DEVICE
An elastic wave device includes a piezoelectric substrate and IDT electrodes including first and second busbars and first and second electrode fingers. An...
2019/0097606 RADIO FREQUENCY FILTER CIRCUIT, DUPLEXER, RADIO FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION APPARATUS
A radio frequency filter circuit (22A) includes a series-arm resonator (22s), a parallel-arm resonator (22p1), a parallel-arm resonator (22p2) that is...
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