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Patent # Description
2019/0096795 METHOD FOR FORMING A HOMOGENEOUS BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE FOR MEMORY
Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA)...
2019/0096794 3DIC PACKAGE INTEGRATION FOR HIGH-FREQUENCY RF SYSTEM
A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no...
2019/0096793 MULTI-ROW WIRING MEMBER FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a permanent resist, a first plating...
2019/0096792 WIRING SUBSTRATE DEVICE
A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end,...
2019/0096791 INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of...
2019/0096790 Dense Redistribution Layers in Semiconductor Packages and Methods of Forming the Same
A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed...
2019/0096789 TAPELESS LEADFRAME PACKAGE WITH UNDERSIDE RESIN AND SOLDER CONTACT
The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed...
2019/0096788 PACKAGE WITH LEAD FRAME WITH IMPROVED LEAD DESIGN FOR DISCRETE ELECTRICAL COMPONENTS AND MANUFACTURING THE SAME
A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad....
2019/0096787 Methods and Devices for Attaching and Sealing a Semiconductor Cooling Structure
A power semiconductor package is disclosed having a base plate with a first surface and an opposing second surface. At least one power semiconductor module can...
2019/0096786 SEMICONDUCTOR PACKAGES THAT INCLUDE A HEAT PIPE FOR EXHAUSTING HEAT FROM ONE OR MORE ENDS OF THE PACKAGE
A semiconductor package includes a package substrate including a fastening section at one end and a connecting terminal section at an opposite end, at least...
2019/0096785 CONFORMABLE HEAT SPREADER
A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing...
2019/0096784 SEMICONDUCTOR DEVICE
A semiconductor device may include: a semiconductor module in which a semiconductor element is sealed in a resin package, and a heat sink is located on at...
2019/0096783 SYSTEM AND METHOD TO ENHANCE SOLDER JOINT RELIABILITY
A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The...
2019/0096782 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region...
2019/0096781 3DIC Packaging with Hot Spot Thermal Management Features
A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and...
2019/0096780 Magnetic Phase Change Material for Heat Dissipation
An electronic component includes an electronic chip and a magnetic phase change material configured to consume energy when changing between different magnetic...
2019/0096779 Semiconductor Device
A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the...
2019/0096778 AIRTIGHT PACKAGE AND METHOD FOR MANUFACTURING SAME
Provided are an airtight package that can increase the bonding strength between the sealing material layer and the container and a method for manufacturing the...
2019/0096777 SEMICODUCTOR WAFER AND METHOD OF BACKSIDE PROBE TESTING THROUGH OPENING IN FILM FRAME
A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center...
2019/0096776 APPARATUSES AND METHODS FOR TSV RESISTANCE AND SHORT MEASUREMENT IN A STACKED DEVICE
Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip...
2019/0096775 FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
2019/0096774 MICRODEVICE TRANSFER SETUP AND INTEGRATION OF MICRO-DEVICES INTO SYSTEM SUBSTRATE
This disclosure is related to integrating pixelated micro devices into a system substrate.
2019/0096773 METHOD OF INSPECTING SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of inspecting a semiconductor substrate includes measuring light intensity of light reflected on the rotating semiconductor substrate, analyzing a...
2019/0096772 Electrically Testable Integrated Circuit Packaging
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final "non-flip chip" circuit...
2019/0096771 METHOD FOR PROTECTING EPITAXIAL LAYER BY FORMING A BUFFER LAYER ON NMOS REGION
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate...
2019/0096770 SEMICONDUCTOR DEVICES
Semiconductor device as provided may include a substrate with an NMOS region and a PMOS region, and a first transistor in the NMOS region that includes a first...
2019/0096769 FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES
A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench...
2019/0096768 FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES
A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench...
2019/0096767 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a...
2019/0096766 MULTI-DEPTH ETCHING IN SEMICONDUCTOR ARRANGEMENT
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed...
2019/0096765 POWER REDUCTION IN FINFET STRUCTURES
The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second...
2019/0096764 Semi-sequential 3D Integration
Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further...
2019/0096763 LASER PROCESSING METHOD
According to one embodiment, a laser processing method includes irradiating a region of a substrate with first laser light having a first pulse width greater...
2019/0096762 Method for Producing at least One Via in a Wafer
A method for producing a via in a wafer includes providing a wafer, comprising silicon. The method includes producing a conductive region, in the form of a...
2019/0096761 Method for Reducing Metal Plug Corrosion and Device
A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a...
2019/0096760 Methods for Reducing Contact Depth Variation in Semiconductor Fabrication
A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure,...
2019/0096759 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure...
2019/0096758 Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same
A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein...
2019/0096757 THIN FILM INTERCONNECTS WITH LARGE GRAINS
The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit...
2019/0096756 METHOD OF CREATING ALIGNED VIAS IN ULTRA-HIGH DENSITY INTEGRATED CIRCUITS
A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask,...
2019/0096755 High Temperature Resistant Backside Metallization for Compound Semiconductors
An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor...
2019/0096754 ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and...
2019/0096753 METHOD TO ENHANCE ELECTRODE ADHESION STABILITY
The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC...
2019/0096752 Via Patterning Using Multiple Photo Multiple Etch
A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a...
2019/0096751 Dual Damascene Process for Forming Vias and Interconnects in an Integrated Circuit Structure
A method of forming interconnects in a semiconductor device is provided. A mask including first and second openings is formed over a non-conductive structure....
2019/0096750 Selective Film Forming Method and Method of Manufacturing Semiconductor Device
A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the...
2019/0096749 IN-LINE PROTECTION FROM PROCESS INDUCED DIELECTRIC DAMAGE
A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a...
2019/0096748 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second...
2019/0096747 Removing Polymer Through Treatment
A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a...
2019/0096746 COMBINED PRODUCTION MEHTOD FOR SEPARATING A NUMBER OF THIN LAYERS OF SOLID MATERIAL FROM A THICK SOLID BODY
Providing a solid body to be split into a number of layers of solid material, introducing or generating defects in the solid body in order to determine a first...
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