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Patent # Description
2019/0096492 HYBRID READ DISTURB COUNT MANAGEMENT
Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of...
2019/0096491 NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME
A nonvolatile memory device includes a plurality of memory cells and a page buffer including a plurality of page buffer units each connected to the plurality...
2019/0096490 PSEUDO SINGLE PASS NAND MEMORY PROGRAMMING
Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level...
2019/0096489 Read-only operation of non-volatile memory module
A non-volatile memory module and a read-only operation of the non-volatile memory module are disclosed. A non-volatile memory module such as a non-volatile...
2019/0096488 NONVOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING THE NONVOLATILE MEMORY DEVICE
A method of programming a non-volatile memory device including a first memory block and a second memory block includes: performing a first program operation on...
2019/0096487 MEMORY SYSTEM
According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell,...
2019/0096486 SEMICONDUCTOR MEMORY DEVICE
In a semiconductor memory device of an embodiment, a write circuit includes an inversion circuit configured to invert write data and output the inverted write...
2019/0096485 CONTROLLER, SEMICONDUCTOR MEMORY DEVICE, AND MEMORY SYSTEM HAVING THE SAME
A controller which controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a randomizer. The...
2019/0096484 APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
2019/0096483 NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory...
2019/0096482 CROSS POINT MEMORY CONTROL
The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL)...
2019/0096481 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a...
2019/0096480 PHASE-CHANGE MEMORY WITH SELECTORS IN BJT TECHNOLOGY AND DIFFERENTIAL-READING METHOD THEREOF
A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a...
2019/0096479 NONVOLATILE METHOD DEVICE AND SENSING METHOD OF THE SAME
A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node...
2019/0096478 SRAM BASED AUTHENTICATION CIRCUIT
A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data...
2019/0096477 Turbo Mode SRAM for High Performance
Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line...
2019/0096476 Low Voltage Bit-Cell
Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four...
2019/0096475 TRANSPOSE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS CONFIGURED FOR HORIZONTAL AND VERTICAL READ OPERATIONS
Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations are disclosed. In one aspect, a transpose SRAM...
2019/0096474 STRAP CELL DESIGN FOR STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY
A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array, a second bit cell array, and a strap cell. The second...
2019/0096473 MEMORY DEVICE AND CONTROL METHOD THEREOF
A method of controlling a memory device including a temperature sensor includes sensing a temperature of the memory device and extracting an extracted...
2019/0096472 MEMORY CHIP HAVING REDUCED BASELINE REFRESH RATE WITH ADDITIONAL REFRESHING FOR WEAK CELLS
A method performed by a memory chip is described. The method includes specially requesting additional refreshes for weak storage cells of the memory chip that...
2019/0096471 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that...
2019/0096470 SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM
A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and...
2019/0096469 SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION
One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command...
2019/0096468 DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method...
2019/0096467 CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric capacitor of a memory cell may be in electronic...
2019/0096466 CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric capacitor of a memory cell may be in electronic...
2019/0096465 VIRTUAL GROUND SENSING CIRCUITRY AND RELATED DEVICES, SYSTEMS, AND METHODS FOR CROSSPOINT FERROELECTRIC MEMORY
Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense...
2019/0096464 VIRTUAL GROUND SENSING CIRCUITRY AND RELATED DEVICES, SYSTEMS, AND METHODS FOR CROSSPOINT FERROELECTRIC MEMORY
Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense...
2019/0096463 CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a...
2019/0096462 ONE-TRANSISTOR SYNAPSE CELL WITH WEIGHT ADJUSTMENT
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a...
2019/0096461 MEMORY DEVICE
According to one embodiment, a memory device includes: a first memory element arranged above a substrate; a first contact portion adjacent to the first memory...
2019/0096460 MEMORY HOLD MARGIN CHARACTERIZATION AND CORRECTION CIRCUIT
An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit...
2019/0096459 MEMORY DEVICES FOR PERFORMING MULTIPLE WRITE OPERATIONS AND OPERATING METHODS THEREOF
A memory device for performing a data write operation based on a multiple write command, an operating method thereof, and an operating method of a memory...
2019/0096458 THREE-DIMENSIONAL (3-D) WRITE ASSIST SCHEME FOR MEMORY CELLS
An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set...
2019/0096457 MEMORY CIRCUIT INCLUDING TRACKING CIRCUIT
A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled...
2019/0096456 QUANTIZING CIRCUITS HAVING IMPROVED SENSING
A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and...
2019/0096455 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a...
2019/0096454 SEMICONDUCTOR DEVICE AND SYSTEM PERFORMING CALIBRATION OPERATION
A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a...
2019/0096453 STACKED MEMORY DEVICE, A SYSTEM INCLUDING THE SAME AND AN ASSOCIATED METHOD
A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of...
2019/0096452 MEMORY MAPPING
Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more...
2019/0096451 DQS-OFFSET AND READ-RTT-DISABLE EDGE CONTROL
Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin...
2019/0096449 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE APPARATUS INCLUDING THE SAME
A nonvolatile memory device includes a memory cell array, a page buffer including a first latch configured to store data to be programmed in a first state, a...
2019/0096448 AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE
A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be...
2019/0096447 NON-VOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME
A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is...
2019/0096446 MEMORY DEVICE INCLUDING BIT LINE SENSE AMPLIFIER FOR CONSTANTLY CONTROLLING SENSING OPERATION
A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier...
2019/0096445 VOLTAGE REFERENCE COMPUTATIONS FOR MEMORY DECISION FEEDBACK EQUALIZERS
A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data...
2019/0096444 CIRCUIT FOR MEMORY SYSTEM AND ASSOCIATED METHOD
A circuit for a memory system including a plurality of memories, including: a plurality of connection traces coupled in series, each connection trace having a...
2019/0096443 BASE UNIT AND DISK DRIVE APPARATUS
Provided is a base unit for use in a disk drive apparatus and to be attached to a cover portion to define an enclosed space to be filled with a gas having a...
2019/0096442 ELASTIC-PLATE FIXING STRUCTURE OF TRAY FOR DATA ACCESSING DEVICE
An elastic-plate fixing structure of a tray for receiving a data accessing device includes a base case and a fastening unit. The base case includes a coupling...
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