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Patent # Description
2019/0095379 SERIAL BUS AUTO-ADDRESSING
A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid...
2019/0095378 SELECT COMMUNICATIONS AND DATA ASPECTS OF POOL AND SPA EQUIPMENT SUCH AS SALT-WATER CHLORINATORS
Methods and systems for effecting electronic communication to, from, and within salt water chlorinators (SWCs) are detailed. Information relating to operating...
2019/0095377 SERIAL CONNECTION BETWEEN MANAGEMENT CONTROLLER AND MICROCONTROLLER
An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard....
2019/0095376 REPLACING MECHANICAL/MAGNETIC COMPONENTS WITH A SUPERCOMPUTER
A supercomputer comprising a memory device and a plurality of interconnected hardware processors capable of performing parallel processing is coupled to a...
2019/0095375 REPLACING MECHANICAL/MAGNETIC COMPONENTS WITH A SUPERCOMPUTER
A supercomputer comprising a memory device and a plurality of interconnected hardware processors capable of performing parallel processing is coupled to a...
2019/0095374 PORTABLE COMPUTING SYSTEM AND PORTABLE COMPUTER FOR USE WITH SAME
A computing system comprising a portable computer and a reader are disclosed. The portable computer is pocket-sized and comprises flash memory, and optionally...
2019/0095373 TRANSFORMATIONAL ARCHITECTURE FOR MULTI-LAYER SYSTEMS
The new architecture disclosed herein exploits advances in system and chip technologies to implement a scalable multi-port open network. Using System-on-a-Chip...
2019/0095372 System, Apparatus And Method For Tunneling Validated Security Information
In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at...
2019/0095371 COMMUNICATION CONTROL UNIT FOR VEHICLE AND COMMUNICATION CONTROL SYSTEM FOR VEHICLE
A communication control unit for a vehicle is configured to be coupled to a first bus that couples control units to each other in the vehicle. The ...
2019/0095370 METHOD FOR INTEGRATING A FURTHER BUS SUBSCRIBER INTO A BUS SYSTEM, AND BUS SYSTEM
A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the...
2019/0095369 PROCESSORS, METHODS, AND SYSTEMS FOR A MEMORY FENCE IN A CONFIGURABLE SPATIAL ACCELERATOR
Systems, methods, and apparatuses relating to a memory fence mechanism in a configurable spatial accelerator are described. In one embodiment, a processor...
2019/0095368 CONFIGURABLE INPUT / OUTPUT CONNECTOR IN A CAMERA
A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral...
2019/0095367 DEVICE MANAGEMENT SYSTEM, DEVICE MANAGER, RELAY MANAGEMENT DEVICE, DEVICE MANAGEMENT METHOD, AND RECORDING MEDIUM
Provided is technology simplifying managing locally connected devices. A device management system configured to connect through a network a device manager and...
2019/0095366 DATA TRANSFER CONTROL DEVICE AND IMAGE FORMING APPARATUS
A data transfer control device includes an acquisition section, an analysis section, a band detection section, a mask output section and a selection section....
2019/0095365 TECHNIQUES FOR REDUCING ACCELERATOR-MEMORY ACCESS COSTS IN PLATFORMS WITH MULTIPLE MEMORY CHANNELS
Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform...
2019/0095364 CONTROLLING METHOD, CHANNEL OPERATING CIRCUIT AND MEMORY SYSTEM FOR EXECUTING MEMORY DIES WITH SINGLE CHANNEL
A controlling method, a channel operating circuit and a memory system for executing a plurality of memory dies with single channel are provided. The plurality...
2019/0095363 HIGH BANDWIDTH LINK LAYER FOR COHERENT MESSAGES
Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol...
2019/0095362 PROGRAMMABLE RADIO TRANSCEIVERS
A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one...
2019/0095361 MEMORY BUS MR REGISTER PROGRAMMING PROCESS
A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the...
2019/0095360 Sorting Memory Address Requests for Parallel Memory Access
Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A...
2019/0095359 PERIPHERAL DEVICE CONTROLLING DEVICE, OPERATION METHOD THEREOF, AND OPERATION METHOD OF PERIPHERAL DEVICE...
A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device...
2019/0095358 Intelligent bluetooth beacon I/O expansion system
Apparatus, methods and system relating to a vehicular telemetry environment for an intelligent Bluetooth beacon I/O expansion of the vehicular telemetry...
2019/0095356 MEMORY SYSTEM AND HANDLES TO MASTER CAPABILITIES
In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to...
2019/0095355 DEVICES AND METHODS FOR SECURED PROCESSORS
Embodiments of the invention provide a computing device comprising one or more processors, each processor comprising one or more processing unit, said one or...
2019/0095354 EXECUTION PROCESS OF BINARY CODE OF FUNCTION SECURED BY MICROPROCESSOR
A method including the loading into registers of a microprocessor of a code line recorded at an address @.sub.j, and then calculating, with a securing hardware...
2019/0095353 PROTECTED DATASETS ON TAPE CARTRIDGES
Examples described herein include a tape drive with a drive memory, an opening, and a key engine. The drive memory is to store a shared secret. The opening is...
2019/0095352 DYNAMIC RECONFIGURATION AND MANAGEMENT OF MEMORY USING FIELD PROGRAMMABLE GATE ARRAYS
Techniques are provided for managing memory hot-add to a computing platform. A system implementing the techniques according to an embodiment includes a Field...
2019/0095351 TECHNOLOGIES FOR A MEMORY ENCRYPTION ENGINE FOR MULTIPLE PROCESSOR USAGES
Technologies for secure memory usage include a computing device having a processor that includes a memory encryption engine and a memory device coupled to the...
2019/0095350 System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption
In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read...
2019/0095349 APPARATUS, SYSTEM, AND METHOD TO DETERMINE A CACHE LINE IN A FIRST MEMORY DEVICE TO BE EVICTED FOR AN INCOMING...
Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory...
2019/0095348 WORKLOAD DETECTION AND MEDIA CACHE MANAGEMENT
Implementations disclosed herein include a method comprising detecting a workload request from a host, estimating a media cache fill-up rate based on the...
2019/0095347 MULTI-PORT SHARED CACHE APPARATUS
An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory....
2019/0095346 ON-DEMAND CACHE MANAGEMENT OF DERIVED CACHE
Techniques related to automatic cache management are disclosed. In some embodiments, one or more non-transitory storage media store instructions which, when...
2019/0095345 EVICTING CLEAN SECURE PAGES WITHOUT ENCRYPTION
Secure memory paging technologies are described. Embodiments of the disclosure may include checking attributes of secure page cache map to determine whether a...
2019/0095344 USING GLOBAL NAMESPACE ADDRESSING IN A DISPERSED STORAGE NETWORK
A method begins with a processing module of a dispersed storage network (DSN) receiving a first data object for storage in the DSN from a requesting entity...
2019/0095343 LOW-LATENCY ACCELERATOR
Methods, apparatus and associated techniques and mechanisms for reducing latency in accelerators. The techniques and mechanisms are implemented in platform...
2019/0095342 Open-Addressing Probing Barrier
An open address probing barrier is utilized in association with a memory container. A starting memory slot is calculated for an item to be found in the memory...
2019/0095341 LOW OVERHEAD MAPPING FOR HIGHLY SEQUENTIAL DATA
Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics...
2019/0095340 DISCONTIGUOUS STORAGE AND CONTIGUOUS RETRIEVAL OF LOGICALLY PARTITIONED DATA
A memory region has logical partitions. Each logical partition has data packages. The memory region discontiguously stores the data packages of the logical...
2019/0095339 SYSTEM CONTROL USING SPARSE DATA
A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a...
2019/0095338 SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, AND SEMICONDUCTOR DEVICE CONTROL METHOD
Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and...
2019/0095337 MANAGING MEMORY ALLOCATION BETWEEN INPUT/OUTPUT ADAPTER CACHES
A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is...
2019/0095336 HOST COMPUTING ARRANGEMENT, REMOTE SERVER ARRANGEMENT, STORAGE SYSTEM AND METHODS THEREOF
A host computing arrangement is provided, which may include a host processor having a host operating system and host kernel associated therewith. The host...
2019/0095335 OPPORTUNISTIC INCREASE OF WAYS IN MEMORY-SIDE CACHE
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of...
2019/0095334 SECURE MEMORY REPARTITIONING TECHNOLOGIES
Secure memory repartitioning technologies are described. Embodiments of the disclosure may include a processing device including a processing core and a memory...
2019/0095333 INDEPENDENT TUNING OF MULTIPLE HARDWARE PREFETCHERS
Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes...
2019/0095332 NEAR MEMORY MISS PREDICTION TO REDUCE MEMORY ACCESS LATENCY
Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If...
2019/0095331 MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPRESSED CACHE LINES
A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical...
2019/0095330 PREEMPTIVE CACHE WRITEBACK WITH TRANSACTION SUPPORT
A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an...
2019/0095329 DYNAMIC PAGE ALLOCATION IN MEMORY
Technology for a system operable to allocate physical pages of memory is described. The system can include a memory side cache, a memory side cache monitoring...
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