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Patent # Description
2019/0103354 INTEGRATED CIRCUIT WITH GUARD RING
An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first...
2019/0103352 SEMICONDUCTOR DEVICE WITH INTEGRATED CAPACITOR AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a capacitor including a first electrode and a second electrode disposed over and electrically insulated from the first...
2019/0103351 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE HAVING CONDUCTIVE STRUCTURE WITH TWIN BOUNDARIES
A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including...
2019/0103350 METHODS OF FORMING SEMICONDUCTOR DEVICES
A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged...
2019/0103349 INTEGRATED EMBEDDED SUBSTRATE AND SOCKET
An apparatus is provided which comprises: a substrate material comprising one or more embedded copper planes, one or more plated through holes through the...
2019/0103348 INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a...
2019/0103347 ELECTRONIC COMPONENT ALIGNMENT DEVICE AND METHOD
A system and method for aligning components is disclosed. A system arranges a plurality of components in a first component alignment. The system places two...
2019/0103346 ELECTRONIC PACKAGE WITH PASSIVE COMPONENT BETWEEN SUBSTRATES
An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate...
2019/0103345 CONSTRAINED CURE COMPONENT ATTACH PROCESS FOR IMPROVED IC PACKAGE WARPAGE CONTROL
An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second...
2019/0103344 POWER CONVERSION DEVICE
To obtain a compact and high output power conversion device by achieving high heat dispersion performance and a reduction in heat generation, and enabling an...
2019/0103343 POWER MODULE FOR VEHICLE
A vehicle power module for converting power includes a lead frame configured to receive power from outside or to output power to the outside and a substrate...
2019/0103342 SEMICONDUCTOR CHIP PACKAGE COMPRISING SUBSTRATE, SEMICONDUCTOR CHIP, AND LEADFRAME AND A METHOD FOR FABRICATING...
A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface....
2019/0103341 ELECTRODE CONNECTION STRUCTURE, LEAD FRAME, AND METHOD FOR FORMING ELECTRODE CONNECTION STRUCTURE
[Problem] To provide an electrode connection structure and the like in which a plurality of elongated leads are arranged in parallel and a longitudinal side...
2019/0103340 SEMICONDUCTOR DEVICE
A semiconductor device is provided with a first insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the...
2019/0103339 BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION
A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk...
2019/0103338 FLEXIBLE SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die...
2019/0103337 FLEXIBLE SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die...
2019/0103336 CERAMIC MODULE FOR POWER SEMICONDUCTOR INTEGRATED PACKAGING AND PREPARATION METHOD THEREOF
A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate...
2019/0103335 ELECTRONIC COMPONENT-EMBEDDED BOARD
There is provided an electronic component-embedded board. The electronic component-embedded board includes: a first insulating layer; a metal layer formed on...
2019/0103334 SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes: a radiator plate; a resin insulating layer provided on the radiator plate; a resin block made of resin and armularly...
2019/0103333 Semiconductor devices, and a Method for Forming a Semiconductor device
A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device...
2019/0103332 WAFER-LEVEL SYSTEM-IN-PACKAGE STRUCTURE AND ELECTRONIC APPARATUS THEREOF
A wafer-level system-in-package structure and an electronic apparatus are provided. The wafer-level system-in-package structure includes a substrate having a...
2019/0103331 NON-MAGNETIC PACKAGE AND METHOD OF MANUFACTURE
A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a...
2019/0103330 SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating substrate, a semiconductor element provided on the insulating substrate, a case frame, a press-fit terminal, and...
2019/0103329 SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes: a case made of resin; an insert terminal including an external terminal portion embedded in the case and having a first...
2019/0103328 WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS
A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut...
2019/0103327 WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS
A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut...
2019/0103326 INDUCED WARPAGE OF A THERMAL CONDUCTOR
Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon...
2019/0103325 Footing Removal in Cut-Metal Process
A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second...
2019/0103324 Methods of Cutting Metal Gates and Structures Formed Thereof
A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is...
2019/0103323 Methods of Cutting Metal Gates and Structures formed Thereof
A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is...
2019/0103322 SILICON AND SILICON GERMANIUM NANOWIRE FORMATION
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more...
2019/0103321 HIGH MOBILITY TRANSISTORS
An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity...
2019/0103320 MIDDLE-OF-LINE SHIELDED GATE FOR INTEGRATED CIRCUITS
Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce...
2019/0103319 METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE
Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a...
2019/0103318 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate. The substrate...
2019/0103317 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and...
2019/0103316 THREE-DIMENSIONAL (3D) INDUCTOR-CAPACITOR (LC) CIRCUIT
Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive...
2019/0103315 METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT
The method of manufacturing a light emitting element includes: temporarily fixing a semiconductor layer of a wafer including a base member and the...
2019/0103314 AUTOMATED TRANSFER AND DRYING TOOL FOR PROCESS CHAMBER
Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe...
2019/0103313 CARRIER SUBSTRATE, PACKAGE, AND METHOD OF MANUFACTURE
A method of manufacturing, a carrier, and a semiconductor package are provided. The method involves depositing a plurality of conductive vias, applying a...
2019/0103312 FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask...
2019/0103311 Metal Gates of Transistors Having Reduced Resistivity
A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric,...
2019/0103310 INTERCONNECT STRUCTURES
The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The...
2019/0103309 FinFET Device and Method of Manufacture
A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed...
2019/0103308 Semiconductor Devices and Methods of Forming
Semiconductor devices and methods of forming are provided. In some embodiments the method includes forming a dielectric layer over a substrate and patterning...
2019/0103307 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure,...
2019/0103306 METHOD FOR FORMING VIAS AND METHOD FOR FORMING CONTACTS IN VIAS
A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer;...
2019/0103305 Metal Routing with Flexible Space Formed Using Self-Aligned Spacer Patterning
A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second...
2019/0103304 DUMMY FIN STRUCTURES AND METHODS OF FORMING SAME
An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from...
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