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Patent # Description
2019/0102341 OBJECT INFORMATION PROCESSING METHOD AND APPARATUS, AND STORAGE MEDIUM
An object information processing method includes obtaining an information creation request. The information creation request carries a first address identifier...
2019/0102340 FILE TRACKING ON CLIENT MACHINES SYNCHRONIZED WITH A CONTENT MANAGEMENT SYSTEM REPOSITORY
Using a first unique identifier of a local file on a client machine associated with a second unique identifier of a content item maintained at a content...
2019/0102339 Multimedia File Sharing Method and Terminal Device
In a method, a terminal device obtains at least one template source file of a first contact in different ways, and when the terminal devices obtains a face...
2019/0102338 PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR HAVING A SEQUENCER DATAFLOW OPERATOR
Systems, methods, and apparatuses relating to a sequencer dataflow operator of a configurable spatial accelerator are described. In one embodiment, an...
2019/0102337 SCALABLE TRAINING OF RANDOM FORESTS FOR HIGH PRECISE MALWARE DETECTION
In one embodiment, a device trains a machine learning-based malware classifier using a first randomly selected subset of samples from a training dataset. The...
2019/0102336 Modular Data Acquisition System
The present invention is a mobile modular data acquisition system including at least one module, and interconnect means, that are adapted to connect a pair of...
2019/0102335 INTEGRATED UNIVERSAL SERIAL BUS (USB) TYPE-C SWITCHING
An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first...
2019/0102334 METHOD, APPARATUS, SYSTEM FOR THUNDERBOLT-BASED DISPLAY TOPOLOGY FOR DUAL GRAPHICS SYSTEMS
Aspects of the embodiments are directed to a ThunderBolt (TBT) input/output (I/O) controller apparatus. The TBT I/O controller apparatus can include an output...
2019/0102333 METHODS AND DEVICES FOR EXTENDING USB 3.0-COMPLIANT COMMUNICATION OVER AN EXTENSION MEDIUM
An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed...
2019/0102332 BUS SYSTEM
A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command...
2019/0102331 MEMORY CHANNEL HAVING MORE THAN ONE DIMM PER MOTHERBOARD DIMM CONNECTOR
A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method...
2019/0102330 COMMUNICATING DATA WITH STACKED MEMORY DIES
Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external...
2019/0102329 ADAPTIVE BUFFERING OF DATA RECEIVED FROM A SENSOR
In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is...
2019/0102328 DETECTION OF A TIME CONDITION RELATIVE TO A TWO-WIRE BUS
A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold...
2019/0102327 CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING
A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to...
2019/0102326 METHOD, APPARATUS, SYSTEM FOR EARLY PAGE GRANULAR HINTS FROM A PCIE DEVICE
Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization...
2019/0102325 MEMORY CONTROL MANAGEMENT OF A PROCESSOR
Systems, apparatuses and methods may provide for technology that conducts a comparison between an identified capability of a memory device and memory usage...
2019/0102324 CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS
Cache behavior for secure memory repartitioning systems is described. Implementations may include a processing core and a memory controller coupled between the...
2019/0102323 VERIFICATION BIT FOR ONE-WAY ENCRYPTED MEMORY
An embodiment of a semiconductor package apparatus may include technology to identify a first encrypted memory alias corresponding to a first portion of memory...
2019/0102322 CROSS-DOMAIN SECURITY IN CRYPTOGRAPHICALLY PARTITIONED CLOUD
Solutions for secure memory access in a computing platform, include a multi-key encryption (MKE) engine as part of the memory interface between processor...
2019/0102321 TECHNIQUES TO PROVIDE ACCESS PROTECTION TO SHARED VIRTUAL MEMORY
Various embodiments are generally directed to techniques for shared virtual memory (SVM) access protection, such as by performing a security check whenever a...
2019/0102320 TIME TRACKING WITH PATROL SCRUB
One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM)...
2019/0102319 MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, MEMORY CONTROL METHOD, AND PROGRAM
To reduce a capacity of a buffer included in a memory controller for managing a replacement area of a memory. Replacement management information for managing a...
2019/0102318 Cache Memory That Supports Tagless Addressing
The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to...
2019/0102317 TECHNOLOGIES FOR FLEXIBLE VIRTUAL FUNCTION QUEUE ASSIGNMENT
Technologies for I/O device virtualization include a computing device with an I/O device that includes a physical function, multiple virtual functions, and...
2019/0102316 MEMORY SYSTEM WITH CORE DIES STACKED IN VERTICAL DIRECTION
A memory system includes N core dies (N: an integer greater than one) stacked in a vertical direction and including N respective memory circuits having a same...
2019/0102315 TECHNIQUES TO PERFORM MEMORY INDIRECTION FOR MEMORY ARCHITECTURES
Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory...
2019/0102314 TAG CACHE ADAPTIVE POWER GATING
An embodiment of a semiconductor package apparatus may include technology to determine a workload characteristic for a tag cache, and adjust a power parameter...
2019/0102313 TECHNIQUES TO STORE DATA FOR CRITICAL CHUNK OPERATIONS
Various embodiments are generally directed to techniques to store data for critical chunk operations, such as by utilizing a spare lane, for instance. Some...
2019/0102312 LAZY INCREMENT FOR HIGH FREQUENCY COUNTERS
A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the...
2019/0102311 ACCELERATOR FABRIC
A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect...
2019/0102310 METHOD AND APPARATUS FOR CONTROL OF A TIERED MEMORY SYSTEM
A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses...
2019/0102309 NV CACHE
Data blocks are cached in a persistent cache ("NV cache") allocated from as non-volatile RAM ("NVRAM"). The data blocks may be accessed in place in the NV...
2019/0102308 METHOD AND DEVICES FOR MANAGING CACHE
Embodiments of the present disclosure relate to a method and apparatus for managing cache. The method comprises determining a cache flush time period of the...
2019/0102307 CACHE TRANSFER TIME MITIGATION
In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical...
2019/0102306 MAINTAINING TRACK FORMAT METADATA FOR TARGET TRACKS IN A TARGET STORAGE IN A COPY RELATIONSHIP WITH SOURCE...
Provided area computer program product, system, and method for maintaining track format metadata for target tracks in a target storage in a copy relationship...
2019/0102305 METHOD AND ELECTRONIC DEVICE FOR ACCESSING DATA
Various embodiments of the present disclosure generally relate to a method and an electronic device for reading data. Specifically, the method comprises...
2019/0102304 METHOD AND APPARATUS FOR CACHE PRE-FETCH WITH OFFSET DIRECTIVES
A method and apparatus for pre-fetching data into a cache using a hardware element that includes registers for receiving a reference for an initial pre-fetch...
2019/0102303 SOFTWARE-TRANSPARENT HARDWARE PREDICTOR FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION
Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein....
2019/0102302 PROCESSOR, METHOD, AND SYSTEM FOR CACHE PARTITIONING AND CONTROL FOR ACCURATE PERFORMANCE MONITORING AND...
Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described...
2019/0102301 TECHNOLOGIES FOR ENFORCING COHERENCE ORDERING IN CONSUMER POLLING INTERACTIONS
Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which...
2019/0102300 APPARATUS AND METHOD FOR MULTI-LEVEL CACHE REQUEST TRACKING
An apparatus and method for multi-level cache request tracking. For example, one embodiment of a processor comprises: one or more cores to execute instructions...
2019/0102299 SYSTEMS, METHODS AND APPARATUS FOR FABRIC DELTA MERGE OPERATIONS TO ENHANCE NVMEOF STREAM WRITES
A method and apparatus for performing a data transfer, which include a selection a data transfer operation mode, based on telemetry data, from a first...
2019/0102298 VARIABLE MODULATION SCHEME FOR MEMORY DEVICE ACCESS OR OPERATION
Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for...
2019/0102297 SYSTEM AND METHOD FOR BROADCAST CACHE INVALIDATION
One embodiment includes a system comprising a repository configured to store objects, an object cache configured to cache objects retrieved from the repository...
2019/0102296 DATA PRESERVATION AND RECOVERY IN A MEMORY COMPONENT
In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the...
2019/0102295 METHOD AND APPARATUS FOR ADAPTIVELY SELECTING DATA TRANSFER PROCESSES FOR SINGLE-PRODUCER-SINGLE-CONSUMER AND...
A method for adaptively performing a set of data transfer processes in a multi-core processor is described. The method may include receiving, by a shared cache...
2019/0102294 SEMICONDUCTOR DEVICE
A semiconductor device includes a decoder configured to receive an extended mode register set (EMRS) code including specific information, and decode the...
2019/0102293 STORAGE SYSTEM WITH INTERCONNECTED SOLID STATE DISKS
An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and...
2019/0102291 DATA STORAGE DEVICE AND METHOD FOR OPERATING NON-VOLATILE MEMORY
Device-based space allocation and host-based mapping table searching are disclosed for operating a non-volatile memory. In response to a write command from a...
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