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Patent # Description
2019/0109120 INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A CHIP RECESS
IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be...
2019/0109119 Package Structures and Methods of Forming the Same
An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side...
2019/0109118 Multi-Chip Fan Out Package and Methods of Forming the Same
A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line...
2019/0109117 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is...
2019/0109116 POWER CONVERSION DEVICE
A first member of a first semiconductor module and a second member of a second semiconductor module are disposed adjacent to each other along a crossing line...
2019/0109115 MICROELECTRONIC INTERPOSER FOR A MICROELECTRONIC PACKAGE
A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in...
2019/0109114 MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE STACK
A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a...
2019/0109113 SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME
The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion...
2019/0109112 Semiconductor Die Attach System and Method
A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at...
2019/0109111 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOF
A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from...
2019/0109110 Shaped Interconnect Bumps in Semiconductor Devices
In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or...
2019/0109109 MULTILAYERS OF NICKEL ALLOYS AS DIFFUSION BARRIER LAYERS
A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a.sub.1. The structure also...
2019/0109108 EXPANDED HEAD PILLAR FOR BUMP BONDS
A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The...
2019/0109107 METHOD AND APPARATUS FOR FORMING BACKSIDE DIE PLANAR DEVICES AND SAW FILTER
Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on...
2019/0109106 SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS
Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least...
2019/0109105 STRUCTURE AND METHOD FOR SEMICONDUCTOR PACKAGING
A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure...
2019/0109104 ELECTRONIC DEVICE HAVING COATED CONTACT PADS
A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g.,...
2019/0109103 Method of Forming a Semiconductor Package and Semiconductor Package
Various embodiments provide a method of forming a semiconductor package. The method includes arranging a semiconductor die and a first substrate, wherein the...
2019/0109102 TRANSISTOR OUTLINE HOUSING WITH HIGH RETURN LOSS
A transistor outline housing is provided that includes a header for an optoelectronic component. The header has electrical feedthroughs in the form of...
2019/0109101 Method and Apparatus for Heat Sinking High Frequency IC with Absorbing Material
A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar...
2019/0109099 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INTEGRATED SUBSTRATE, AND ELECTRONIC DEVICE
The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, an integrated substrate, and an electronic device...
2019/0109098 Semiconductor Device Structure Comprising a Plurality of Metal Oxide Fibers and Method for Forming the Same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive...
2019/0109097 SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM
A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some...
2019/0109096 Semiconductor Device With shield for Electromagnetic interference
A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding...
2019/0109095 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a...
2019/0109094 PACKAGE SUBSTRATE PROCESSING METHOD AND PROTECTIVE TAPE
A package substrate processing method for processing a package substrate in which a plurality of semiconductor chips on a wiring substrate are collectively...
2019/0109093 INDUSTRIAL CHIP SCALE PACKAGE FOR MICROELECTRONIC DEVICE
A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically...
2019/0109092 POSITIONING STRUCTURE HAVING POSITIONING UNIT
A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded...
2019/0109091 COMPONENT-EMBEDDED SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND HIGH-FREQUENCY MODULE
A method of manufacturing a component-embedded substrate includes a resist forming step in which a patterning resist is formed on a support, a patterning step...
2019/0109090 INTERCONNECTION STRUCTURE LINED BY ISOLATION LAYER
A semiconductor device includes: a first conductive structure that comprises a first portion having sidewalls and a bottom surface, wherein the first...
2019/0109089 FUSE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion;...
2019/0109088 LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND...
A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on...
2019/0109087 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying...
2019/0109086 Semiconductor Device and Method for Fabricating the Same
Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of...
2019/0109085 PRINTED WIRING BOARD
A printed wiring board includes a first build-up layer having first insulating layer, conductor layer and via conductor, a second build-up layer formed on the...
2019/0109084 CHIP PACKAGES WITH SINTERED INTERCONNECTS FORMED OUT OF PADS
The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal...
2019/0109083 Packages with Si-Substrate-Free Interposer and Method Forming Same
A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked...
2019/0109082 ORGANIC INTERPOSER AND METHOD FOR MANUFACTURING ORGANIC INTERPOSER
There are provided an organic interposer capable of improving insulation reliability and a method for manufacturing the organic interposer. An organic...
2019/0109081 METHODS OF PROCESSING SEMICONDUCTOR DEVICES
Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening...
2019/0109080 ELECTRONIC DEVICES HAVING TAPERED EDGE WALLS
An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of...
2019/0109079 METHODS OF PROCESSING SEMICONDUCTOR DEVICES
Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening...
2019/0109078 THRYSITOR AND THERMAL SWITCH DEVICE AND ASSEMBLY TECHNIQUES THEREFOR
A device may include a lead frame, where the lead frame includes a central portion, and a side pad, the side pad being laterally disposed with respect to the...
2019/0109077 SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes a first semiconductor element, a second semiconductor element, and a metal pattern formed on the second semiconductor...
2019/0109076 Pre-Molded Leadframes in Semiconductor Devices
In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first...
2019/0109075 Inductively Coupled Microelectromechanical System Resonator
An integrated circuit package includes a first die that has a microelectromechanical system (MEMS) resonator coupled to a coil. A second die includes a coil...
2019/0109074 DIE ATTACH SURFACE COPPER LAYER WITH PROTECTIVE LAYER FOR MICROELECTRONIC DEVICES
A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a...
2019/0109073 ELECTRICAL CABLE
An electrical cable includes at least two wires extending side by side along a longitudinal cable direction. The wires are electrically insulated from each...
2019/0109072 Integrated Circuit Package Having A Raised Lead Edge
An integrated circuit package includes a lead frame having a first surface, a second opposing surface, at least one die attach portion configured to support at...
2019/0109071 BASE BODY WITH SOLDERED-ON GROUND PIN, METHOD FOR ITS PRODUCTION AND USES THEREOF
The present disclosure relates to components, such as base bodies, for feed-through elements including a metallic base body, at least one through-opening for...
2019/0109070 Rivetless Lead Fastening for a Semiconductor Package
A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically...
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