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Patent # Description
2019/0108156 INTERFACE CIRCUIT AND PACKET TRANSMISSION METHOD THEREOF
A packet transmission method includes packaging a plurality of data in the form of a payload; storing information on whether the plurality of data are packaged...
2019/0108155 BRIDGE CONNECTING APPARATUS, COMMUNICATION CONTROL SYSTEM, METHOD AND PROGRAM
A bridge connecting apparatus comprises: a connection state control part that controls a first connection state between the bridge connecting apparatus and the...
2019/0108154 METHOD AND APPARATUS FOR POWER REDUCTION FOR DATA MOVEMENT
A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last...
2019/0108153 Electronic Device And Communication Method Thereof
An electronic device includes a case containing a universal serial bus (USB) transmission port, an embedded control unit, a central processing unit, a power...
2019/0108152 CONFIGURABLE HARDWARE ACCELERATORS
In various embodiments, a configurable hardware accelerator is provided. The configurable accelerator may include a transmit direct memory access (DMA) engine,...
2019/0108151 BRIDGE DEVICE AND DATA TRANSFERRING METHOD
A bridge device includes a first physical layer circuit, a first buffer memory, a DMA controller, and a processor. The first physical layer circuit is...
2019/0108150 SEMICONDUCTOR DEVICE
A semiconductor device in which, in principle, plural interrupt request signals can be inputted to a single interrupt terminal is provided. In the...
2019/0108149 I3C IN-BAND INTERRUPTS DIRECTED TO MULTIPLE EXECUTION ENVIRONMENTS
Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described. A master device coupled to the serial bus...
2019/0108148 Data Transmission System and Data Transmission Method
A data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching...
2019/0108147 INNER AND OUTER CODE GENERATOR FOR VOLATILE MEMORY
A system includes a volatile memory to store data and a memory controller to manage the data in the volatile memory. The memory controller includes an inner...
2019/0108146 MULTI-PROCESSOR SYSTEM INCLUDING MEMORY SHARED BY MULTI-PROCESSOR AND METHOD THEREOF
A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data...
2019/0108145 DUAL IN-LINE MEMORY MODULE (DIMM) PROGRAMMABLE ACCELERATOR CARD
A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may...
2019/0108144 MUTUAL EXCLUSION IN A NON-COHERENT MEMORY HIERARCHY
Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple...
2019/0108143 Method and Apparatus for In-Band Priority Adjustment Forwarding in a Communication Fabric
Systems, apparatuses, and methods for implementing priority adjustment forwarding are disclosed. A system includes at least one or more processing units, a...
2019/0108142 ACCESS MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM, AND RECORDING MEDIUM
To appropriately access various portions of a concealed graph while suppressing a processing load. Provided is an access management method in which a computer...
2019/0108141 SYSTEM AND METHOD FOR DETERRING MALICIOUS NETWORK ATTACKS
A system and method for deterring malicious network attacks. The system and method is configured to execute instructions on at least one of the processors to...
2019/0108140 SMART CONTRACT CREATION AND MONITORING FOR EVENT IDENTIFICATION IN A BLOCKCHAIN
An example operation may include one or more of identifying a smart contract, processing the smart contract to create a smart contract definition, determining...
2019/0108139 CLIENT-SIDE PERSISTENT CACHING FRAMEWORK
A system includes reception of a first request to synchronize content from the persistent memory system to the volatile memory system, and, in response to the...
2019/0108138 APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BETWEEN MULTIPLE CACHE LEVELS
A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first...
2019/0108137 METHOD AND APPARATUS FOR JOURNAL AWARE CACHE MANAGEMENT
An intelligent journal-aware caching manager for journaled data is provided. The caching manager ensures that data is not duplicated in a write-ahead-log...
2019/0108136 MEMORY SYSTEM AND OPERATION METHOD THEREOF
A memory system includes a nonvolatile memory device including a plurality of memory blocks; and a controller including a command queue adapted to store a...
2019/0108135 INCREASING THE SCOPE OF LOCAL PURGES OF STRUCTURES ASSOCIATED WITH ADDRESS TRANSLATION
Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues...
2019/0108134 METHOD FOR ACCESSING ENTRY IN TRANSLATION LOOKASIDE BUFFER TLB AND PROCESSING CHIP
A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one...
2019/0108133 ADDRESS TRANSLATION FOR SENDING REAL ADDRESS TO MEMORY SUBSYSTEM IN EFFECTIVE ADDRESS BASED LOAD-STORE UNIT
Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a...
2019/0108132 ADDRESS TRANSLATION FOR SENDING REAL ADDRESS TO MEMORY SUBSYSTEM IN EFFECTIVE ADDRESS BASED LOAD-STORE UNIT
Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a...
2019/0108131 METHOD FOR PERFORMING ACCESS MANAGEMENT IN A MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF,...
A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are...
2019/0108130 System, Apparatus And Method For Multi-Cacheline Small Object Memory Tagging
In one embodiment, a method includes: in response to a sub-cacheline memory access request, receiving a data-line from a memory coupled to a processor;...
2019/0108129 INFORMATION PROCESSING METHOD AND DEVICE, AND METHOD AND DEVICE FOR DISPLAYING DYNAMIC INFORMATION
A plurality of types of user data are collected and stored into a plurality of data queues, where each data queue of the plurality of data queues has a...
2019/0108128 MODE SWITCHING FOR INCREASED OFF-CHIP BANDWIDTH
Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a...
2019/0108127 READ OPEATION REDIRECT
Example implementations relate to read operation redirect. For example, a system according in the present disclosure may include a data storage device...
2019/0108126 NON-COHERENT READ IN A STRONGLY CONSISTENT CACHE SYSTEM FOR FREQUENTLY READ BUT RARELY UPDATED DATA
A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent...
2019/0108125 NON-COHERENT READ IN A STRONGLY CONSISTENT CACHE SYSTEM FOR FREQUENTLY READ BUT RARELY UPDATED DATA
A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent...
2019/0108124 SHARED BUFFERED MEMORY ROUTING
A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier...
2019/0108123 SELECTION OF VARIABLE MEMORY-ACCESS SIZE
A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive...
2019/0108122 UNMAP TO INITIALIZE SECTORS
Examples disclosed herein relate to unmapping sectors of a solid-state drive to initialize the sectors. The sectors include a data portion and a protection...
2019/0108121 MEMORY SYSTEMS FOR DATA COLLECTION AND COMPRESSION IN A STORAGE DEVICE
Memory systems may include a storage device comprising a first memory; a processor; and a second memory. The memory systems may be configured to read first...
2019/0108120 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage...
2019/0108119 NON-VOLATILE MEMORY WITH ADAPTIVE WEAR LEVELING
A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile...
2019/0108118 COMPUTER SYSTEM TESTING
Computer-implemented methods and apparatuses for application testing are provided. Such apparatuses may include a data repository that stores a copy of at...
2019/0108116 ENABLING ATTRIBUTES FOR CONTAINERIZATION OF APPLICATIONS
Implementations of the disclosure include a framework to provide an optimal execution environment for applications in software containers. In one...
2019/0108115 APPLICATION REGRESSION DETECTION IN COMPUTING SYSTEMS
Computing systems, devices, and associated methods of detecting application regression in a distributed computing system are disclosed herein. In one...
2019/0108114 PRESENTING COLLABORATION ACTIVITIES
Systems and methods for presenting relevant collaboration activity to a collaboration system user. A method embodiment commences upon identifying user events...
2019/0108113 SELF-REPORTING GLOBAL MIRROR PERFORMANCE ON A CONSISTENCY GROUP BOUNDARY
A method, computer system, and a computer program product for collecting performance data on a consistency group boundary is provided. The present invention...
2019/0108112 SYSTEM AND METHOD FOR GENERATING A LOG ANALYSIS REPORT FROM A SET OF DATA SOURCES
Disclosed is a log analysis tool for generating a log analysis report upon analyzing log data received from a set of log data sources. An input module receives...
2019/0108111 BIT ERROR RATE PREDICTION
An apparatus to derive a symbol error rate of an interconnect under test from a detector error rate of the interconnect, including: an error storage buffer; an...
2019/0108110 SYSTEM AND METHOD FOR AUTOMATED INTEGRATION AND STRESS TESTING OF HARDWARE AND SOFTWARE SERVICE IN MANAGEMENT...
Systems and methods for automated integration and stress testing of hardware and software services in a management controller using a containerized toolbox....
2019/0108109 Technology To Provide Fault Tolerance For Elliptic Curve Digital Signature Algorithm Engines
A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a...
2019/0108108 MEMORY MANAGEMENT
The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of...
2019/0108107 TIME-BASED CHECKPOINT TARGET FOR DATABASE MEDIA RECOVERY
A method, apparatus, and system for a time-based checkpoint target is provided for standby databases. Change records received from a primary database are...
2019/0108106 FAILOVER OF VIRTUAL DEVICES IN A SCALABLE INPUT/OUTPUT (I/O) VIRTUALIZATION (S-IOV) ARCHITECTURE
Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical...
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