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Patent # Description
2019/0221592 OPTOELECTRONICS AND CMOS INTEGRATION ON GOI SUBSTRATE
A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an...
2019/0221591 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE USING THE SAME
The present disclosure relates to an array substrate, manufacturing method thereof and display device using the same. The method for manufacturing the array...
2019/0221590 ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE PROVIDED WITH ACTIVE MATRIX SUBSTRATE
Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection...
2019/0221589 DISPLAY PANEL AND METHOD FOR FABRICATING DISPLAY PANEL
A method for manufacturing a display panel to comprise light emitting elements which together present a flat and wrinkle-free top surface includes a substrate,...
2019/0221588 ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises...
2019/0221587 THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AS WELL AS DISPLAY DEVICE
The present invention is related to a field of display technology, and in particular to a thin film transistor array substrate, which comprises a glass...
2019/0221586 LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third...
2019/0221585 ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE AND TOUCH PANEL DISPLAY DEVICE INCLUDING SAME
Provided is an active matrix substrate in which differences of parasitic capacitances among lead-out lines connected with signal lines can be reduced, as well...
2019/0221584 DISPLAY APPARATUS
A display apparatus includes a substrate, a display unit, a pad portion, and a connection wire. The display unit is on the substrate. The display unit includes...
2019/0221583 DRIVE DEVICE AND DISPLAY DEVICE
Disclosed is a drive device and a display device. In the drive device, a first substrate row driving circuit is disposed on one side of a scan line array and...
2019/0221582 SEMICONDUCTOR MEMORY DEVICE INCLUDING A SLIT
A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first...
2019/0221581 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first...
2019/0221580 Methods of Filling Horizontally-Extending Openings of Integrated Assemblies
Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The...
2019/0221579 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns...
2019/0221578 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME
According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor...
2019/0221577 VERTICAL INTERCONNECT METHODS FOR STACKED DEVICE ARCHITECTURES USING DIRECT SELF ASSEMBLY WITH HIGH OPERATIONAL...
An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a...
2019/0221576 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME
A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third...
2019/0221575 THREE-DIMENSIONAL FLAT INVERSE NAND MEMORY DEVICE AND METHOD OF MAKING THE SAME
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another...
2019/0221574 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OFFSET COLUMN STAIRS AND METHOD OF MAKING THE SAME
A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory...
2019/0221573 SEMICONDUCTOR DEVICE
According to one embodiment, there is provided a semiconductor device including a first laminated body, a first semiconductor columnar member, a first gate...
2019/0221572 SEMICONDUCTOR MEMORY DEVICES
A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a...
2019/0221571 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the...
2019/0221570 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and...
2019/0221569 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line...
2019/0221568 Memory Arrays
Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along...
2019/0221567 MEMORY CELLS, SEMICONDUCTOR DEVICES COMPRISING MEMORY CELLS, AND RELATED SYSTEMS
A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel...
2019/0221566 CIRCUIT DEVICE AND ELECTRONIC APPARATUS
An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the...
2019/0221565 CONTACT FORMATION IN SEMICONDUCTOR DEVICES
A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer....
2019/0221564 SEMICONDUCTOR DEVICE
Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate...
2019/0221563 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending...
2019/0221562 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes...
2019/0221561 INTEGRATED CIRCUITS AND DEVICES WITH INTERLEAVED TRANSISTOR ELEMENTS, AND METHODS OF THEIR FABRICATION
A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in...
2019/0221560 DEVICE INTEGRATED WITH DEPLETION-MODE JUNCTION FIELF-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which...
2019/0221559 INDIRECT READOUT FET
A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed...
2019/0221558 THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF
Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following...
2019/0221557 THREE-DIMENSIONAL MEMORY DEVICE HAVING SUPPORT-DIE-ASSISTED SOURCE POWER DISTRIBUTION AND METHOD OF MAKING THEREOF
A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory...
2019/0221556 DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively...
2019/0221555 LIGHT EMITTING DEVICE PACKAGE
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom,...
2019/0221554 Opto-Coupler With Field-Shaping End Caps
An opto-coupler includes a housing having end walls configured to have high-voltage (HV) input and output conductors protruding therethrough. The opto-coupler...
2019/0221553 HEXAGONAL PACKING LASER ABLATION
A substrate has a first side and an opposing second side. The opposing second side has a first portion and a second portion. The substrate is at least...
2019/0221552 EFFICIENTLY MICRO-TRANSFER PRINTING MICRO-SCALE DEVICES ONTO LARGE-FORMAT SUBSTRATES
A method of making a micro-transfer printed system includes providing a source wafer having a plurality of micro-transfer printable source devices arranged at...
2019/0221551 LIGHT EMITTING APPARATUS, ILLUMINATION APPARATUS AND DISPLAY APPARATUS
A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper...
2019/0221550 LIGHT-EMITTING DEVICE
A light-emitting device having light-emitting elements with high operation stability and light extraction efficiency is provided. The light-emitting device...
2019/0221549 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first chip to restrict current flow in a first direction through a current path; a second chip to restrict the current flow...
2019/0221548 HYBRID BOND PAD STRUCTURE
In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality...
2019/0221547 DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK
Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer...
2019/0221546 Stacking Integrated Circuits containing Serializer and Deserializer blocks using Through Silicon Via
Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via...
2019/0221545 MULTI-LAYER CHIP AND FABRICATION METHOD THEREOF
A multi-layer chip and a fabrication method thereof are disclosed. The method includes: bonding a first chip having a first metal layer to a second chip having...
2019/0221543 SEMICONDUCTOR PACKAGES INCLUDING A MULTI-CHIP STACK AND METHODS OF FABRICATING THE SAME
Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second...
2019/0221542 SEMICONDUCTOR PACKAGES INCLUDING CHIP STACKS
A semiconductor package may include a first chip stack, a second chip stack, and a third chip stack. The third chip stack may include third semiconductor...
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