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| Patent # | Description |
|---|---|
| US-9,779,825 |
Method for reading an EEPROM and corresponding device One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and... |
| US-9,779,824 |
NAND flash memory comprising current sensing page buffer Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first... |
| US-9,779,823 |
Secure erase of non-volatile memory In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion... |
| US-9,779,822 |
Memory devices and methods of their operation during a programming
operation Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected... |
| US-9,779,821 |
Fast programming memory device In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one... |
| US-9,779,820 |
Non-volatile memory and programming method thereof A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first... |
| US-9,779,819 |
Connecting memory cells to a data line sequentially while applying a
program voltage to the memory cells In an example, a programming method includes applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of... |
| US-9,779,818 |
Adaptation of high-order read thresholds A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations... |
| US-9,779,817 |
Boosting channels of memory cells to reduce program disturb A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected... |
| US-9,779,816 |
Apparatus and methods including source gates Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor... |
| US-9,779,815 |
Method for writing in an EEPROM memory and corresponding device A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory... |
| US-9,779,814 |
Non-volatile static random access memory devices and methods of operations Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access... |
| US-9,779,813 |
Phase change memory array architecture achieving high write/read speed A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring... |
| US-9,779,812 |
Semiconductor memory device According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell... |
| US-9,779,811 |
Apparatuses and methods for efficient write in a cross-point array A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and... |
| US-9,779,810 |
Adjustable writing circuit A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse,... |
| US-9,779,809 |
Resistive semiconductor memory device and operation method thereof A semiconductor memory device includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected... |
| US-9,779,808 |
Resistance random access memory device and method for operating same A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects... |
| US-9,779,807 |
Non-volatile memory using bi-directional resistive elements A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second... |
| US-9,779,806 |
Resistive memory sensing methods and devices Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of... |
| US-9,779,805 |
Phase change memory device A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an... |
| US-9,779,804 |
Flash memory system An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one... |
| US-9,779,803 |
Memory circuit with write-bypass portion One example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass... |
| US-9,779,802 |
Memory apparatus and write failure responsive negative bitline voltage
write assist circuit thereof A write assist circuit includes a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection... |
| US-9,779,801 |
Method and control circuit for memory macro A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking... |
| US-9,779,800 |
Timing control circuit shared by a plurality of banks Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first... |
| US-9,779,799 |
Semiconductor device having input/output line drive circuit and
semiconductor system including the same A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal.... |
| US-9,779,798 |
Systems, methods, and computer programs for providing row tamper
protection in a multi-bank memory cell array Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation... |
| US-9,779,797 |
Non-volatile memory device A non-volatile memory device according to an embodiment includes a first conductive layer, a second conductive layer including metal nitride, the metal nitride... |
| US-9,779,796 |
Redundancy array column decoder for memory Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other... |
| US-9,779,795 |
Magnetic random access memory (MRAM) and method of operation A memory device includes a first line coupled to a first terminal of a first memory cell, a second bit line coupled to a first terminal of a second memory cell,... |
| US-9,779,794 |
Techniques for forming spin-transfer torque memory (STTM) elements having
annular contacts Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The... |
| US-9,779,793 |
Magnetic tunnel junction memory device A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device... |
| US-9,779,792 |
Register file with read ports clustered by entry A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory... |
| US-9,779,791 |
Apparatuses and methods involving accessing distributed sub-blocks of
memory cells Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in... |
| US-9,779,790 |
Nonvolatile memory device and method of driving word line of the
nonvolatile memory A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a... |
| US-9,779,789 |
Comparison operations in memory The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of... |
| US-9,779,788 |
Sub-threshold enabled flash memory system A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more... |
| US-9,779,787 |
Systems and methods for processing data The digital signal processor includes a DRAM including multiple memory cells configured to store data in a parasitic capacitor and a core logic configured to... |
| US-9,779,786 |
Tensor operations and acceleration A system includes global memory circuitry configured to store input tensors and output tensors. Row data paths are each connected to an output port of the... |
| US-9,779,785 |
Computer architecture using compute/storage tiles A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory... |
| US-9,779,784 |
Apparatuses and methods for performing logical operations using sensing
circuitry The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an... |
| US-9,779,783 |
Latching current sensing amplifier for memory array A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are... |
| US-9,779,782 |
Semiconductor device and electronic device In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a... |
| US-9,779,781 |
Memory module battery backup Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup... |
| US-9,779,780 |
Damping vibrations within storage device testing systems A storage device test slot includes a housing. The housing defines a test compartment for receiving a storage device for testing. One or more tuned mass dampers... |
| US-9,779,779 |
Disk device and method of manufacturing disk device According to one embodiment, a disk device includes a disk-shaped recording medium, a head which processes data on the recording medium, and a housing... |
| US-9,779,778 |
Method and apparatus for enabling an application to cooperate with running
of a program The present invention provides a method and apparatus for enabling an application to cooperate with the running of a program. According to the invention, the... |
| US-9,779,777 |
Synchronization of frame rate to a detected cadence in a time lapse image
sequence using sampling A frame rate is synchronized to a detected cadence in order to generate an output image sequence that is substantially stabilized. In an in-camera process, a... |
| US-9,779,776 |
Optical disk reproducing device, reproducing circuit of the same, and
reproducing method of optical disk The present invention suppresses audio skipping. A frame number acquisition unit 102 acquires a current frame number S11. An audio data acquisition unit 104... |
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