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| Patent # | Description |
|---|---|
| US-9,806,070 |
Semiconductor device layout, memory device layout, and method of
manufacturing semiconductor device A layout of a semiconductor device includes active area regions, gate electrodes crossing the plurality of active area regions, spacers along sides of the... |
| US-9,806,069 |
Semiconductor device and method of manufacturing A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is... |
| US-9,806,068 |
Semiconductor device Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the... |
| US-9,806,067 |
Die-die stacking A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to... |
| US-9,806,066 |
Semiconductor package including exposed connecting stubs A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality... |
| US-9,806,064 |
Package with multiple plane I/O structure A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a... |
| US-9,806,063 |
Reinforced wafer level package comprising a core layer for reducing stress
in a solder joint and improving... Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the... |
| US-9,806,062 |
Methods of packaging semiconductor devices and packaged semiconductor
devices Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit... |
| US-9,806,061 |
Bumpless wafer level fan-out package An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an... |
| US-9,806,060 |
Flexible packages including chips A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first... |
| US-9,806,059 |
Multi-stack package-on-package structures Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked... |
| US-9,806,058 |
Chip package having die structures of different heights and method of
forming same Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip... |
| US-9,806,057 |
Chip arranging method A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark... |
| US-9,806,056 |
Method of packaging integrated circuits Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of... |
| US-9,806,055 |
Chip-on-wafer package and method of forming same A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past... |
| US-9,806,054 |
Flexible substrate holder, device and method for detaching a first
substrate A flexible substrate mount for holding a first substrate when the first substrate is being detached from a second substrate, and detachment means for debonding... |
| US-9,806,053 |
Semiconductor package A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate... |
| US-9,806,052 |
Semiconductor package interconnect A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding... |
| US-9,806,051 |
Ultra-thin embedded semiconductor device package and method of
manufacturing thereof A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the... |
| US-9,806,050 |
Method of fabricating package structure A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in... |
| US-9,806,049 |
Semiconductor device In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film... |
| US-9,806,048 |
Planar fan-out wafer level packaging A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and... |
| US-9,806,047 |
Wafer level device and method with cantilever pillar structure A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar... |
| US-9,806,045 |
Interconnection structure including a metal post encapsulated by solder
joint having a concave outer surface A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a... |
| US-9,806,044 |
Bonding film for signal communication between central chip and peripheral
chips and fabricating method thereof A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second... |
| US-9,806,043 |
Method of manufacturing molded semiconductor packages having an optical
inspection feature A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main... |
| US-9,806,042 |
Strain reduced structure for IC packaging A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio... |
| US-9,806,041 |
Method for processing an electronic component and an electronic component According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include:... |
| US-9,806,040 |
Antenna in embedded wafer-level ball-grid array package A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over... |
| US-9,806,039 |
Amplifier In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to... |
| US-9,806,038 |
Reinforcement structure and method for controlling warpage of chip mounted
on substrate A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the... |
| US-9,806,037 |
Device for prevention of integrated circuit chip counterfeiting A timer including a sensor and a radiation source is used to prevent counterfeiting of integrated circuits. The timer confirms the date code of the integrated... |
| US-9,806,036 |
Semiconductor wafer, semiconductor structure and method of manufacturing
the semiconductor wafer A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first... |
| US-9,806,035 |
Semiconductor device A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for... |
| US-9,806,034 |
Semiconductor device with protected sidewalls and methods of manufacturing
thereof A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a... |
| US-9,806,033 |
Noise shielding techniques for ultra low current measurements in
biochemical applications A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a... |
| US-9,806,032 |
Integrated circuit structure with refractory metal alignment marker and
methods of forming same The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor... |
| US-9,806,031 |
Monitor method for process control in a semiconductor fabrication process A monitor method for process control in a semiconductor fabrication process is disclosed. A first alignment mark is formed in a layer on a substrate, and its... |
| US-9,806,030 |
Prototyping of electronic circuits with edge interconnects In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities... |
| US-9,806,029 |
Transistor arrangement with semiconductor chips between two substrates An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface... |
| US-9,806,028 |
Semiconductor memory device A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and... |
| US-9,806,027 |
Semiconductor device A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern... |
| US-9,806,026 |
Self repairing process for porous dielectric materials The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous... |
| US-9,806,025 |
SOI wafers with buried dielectric layers to prevent Cu diffusion An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor... |
| US-9,806,024 |
Simultaneous formation of liner and metal conductor An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench... |
| US-9,806,023 |
Selective and non-selective barrier layer wet removal A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer,... |
| US-9,806,022 |
Method for making semiconductor device with stacked analog components in
back end of line (BEOL) regions A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first... |
| US-9,806,021 |
Manufacturing method of a semiconductor device and method for creating a
layout thereof A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a... |
| US-9,806,020 |
Semiconductor device A semiconductor device that includes a first wiring, a second wiring, and a first number of first resistance elements that are connected in parallel between the... |
| US-9,806,019 |
Integrated circuit with power saving feature An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line... |
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