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Patent # Description
US-9,922,978 Semiconductor structure with recessed source/drain structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a...
US-9,922,977 Transistor with threshold voltage set notch and method of fabrication thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced .sigma.V.sub.T...
US-9,922,976 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack...
US-9,922,975 Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing...
An integrated circuit includes a first semiconductor fin, a first epitaxy structure, and at least two first dielectric fin sidewall structures. The first...
US-9,922,974 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the...
US-9,922,973 Switches with deep trench depletion and isolation structures
The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods...
US-9,922,972 Embedded silicon carbide block patterning
A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a...
US-9,922,971 Integration of analog transistor
An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of...
US-9,922,970 Interposer having stacked devices
An apparatus includes a substrate and an interposer associated with the substrate. The apparatus further includes a first device disposed within the substrate...
US-9,922,969 Integrated circuits having transistors with high holding voltage and methods of producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a source in...
US-9,922,968 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill...
US-9,922,967 Multilevel template assisted wafer bonding
Fabricating a multilevel composite semiconductor structure includes providing a first substrate comprising a first material; dicing a second substrate to...
US-9,922,966 Display module and system applications
A display module and system applications including a display module are described. The display module may include a display substrate including a front surface,...
US-9,922,965 Manufacturing methods semiconductor packages including through mold connectors
A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first...
US-9,922,964 Package structure with dummy die
A package structure and method for forming the same are provided. The package structure includes a substrate, and a device die formed over the substrate. The...
US-9,922,963 Light-emitting device
A light-emitting device includes a substrate, a light-emitting component, a wavelength conversion component, an adhesive and a reflective layer. The...
US-9,922,962 Cooling system for 3D IC
A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a...
US-9,922,961 Semiconductor device, manufacturing method for semiconductor device, and electronic device
There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a...
US-9,922,960 Packaging structure of substrates connected by metal terminals
A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first...
US-9,922,959 Semiconductor device
A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of...
US-9,922,957 Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate, a first electrode located on an upper surface of the substrate, and a second electrode located on a lower surface...
US-9,922,956 Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional...
A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or...
US-9,922,955 Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV...
A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die,...
US-9,922,954 Method for performing direct bonding between two structures
This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed; b)...
US-9,922,953 Process for producing a structure by assembling at least two elements by direct adhesive bonding
A method for producing a structure by direct bonding of two elements, the method including: production of the elements to be assembled and assembly of the...
US-9,922,952 Method for producing semiconductor device, and wire-bonding apparatus
A method of manufacturing a semiconductor device is provided. A bonding tool with a wire tail extending out of the tip thereof is lowered to bring the tip of...
US-9,922,951 Integrated circuit wafer integration with catalytic laminate or adhesive
A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the...
US-9,922,950 Method and structure for wafer-level packaging
A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on...
US-9,922,949 Semiconductor device and method
Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate...
US-9,922,948 Semiconductor device with modified pad spacing structure
A semiconductor device is provided, including a substrate, an interconnection structure formed on the substrate, a first top conductive layer formed on the...
US-9,922,947 Bonding pad structure over active circuitry
Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a...
US-9,922,946 Method of manufacturing a semiconductor package having a semiconductor chip and a microwave component
A method of manufacturing a semiconductor device package includes placing a semiconductor chip on a carrier, covering the semiconductor chip with an...
US-9,922,945 Methods, circuits and systems for a package structure having wireless lateral connections
A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable...
US-9,922,944 Method for manufacturing semiconductor device
A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is...
US-9,922,943 Chip-on-substrate packaging on carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a...
US-9,922,942 Support for long channel length nanowire transistors
A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire...
US-9,922,941 Thin low defect relaxed silicon germanium layers on bulk silicon substrates
A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain...
US-9,922,940 Semiconductor device including air gaps between interconnects and method of manufacturing the same
A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on...
US-9,922,939 Wafer level shielding in multi-stacked fan out packages and methods of forming same
An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the...
US-9,922,938 Semiconductor device package integrated with coil for wireless charging and electromagnetic interference...
The present disclosure relates to a semiconductor device package which includes a carrier, an electronic component disposed on the carrier, and a package body...
US-9,922,937 Self-shielded die having electromagnetic shielding on die surfaces
A self-shielded die includes a substrate, an electronic device attached to the substrate, one or more electrical pads disposed on a bottom surface of the...
US-9,922,936 Semiconductor lithography alignment feature with epitaxy blocker
A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V...
US-9,922,935 Semiconductor package and method of fabricating the same
A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may...
US-9,922,934 Semiconductor manufacturing process and package carrier
A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a...
US-9,922,933 Method of positioning elements, particularly optical elements, on the back side of a hybridized-type infrared...
A method of positioning elements or additional technological levels on the incident surface of an infrared detector of hybridized type, said detector being...
US-9,922,932 Resin structure having electronic component embedded therein, and method for manufacturing said structure
In a resin structure including a resin molded body and a plurality of electronic components embedded in the resin molded body, (i) the resin molded body has a...
US-9,922,931 Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect...
An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the...
US-9,922,930 Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
US-9,922,929 Self aligned interconnect structures
The present disclosure relates to semiconductor structures and, more particularly, to self aligned interconnect structures and methods of manufacture. The...
US-9,922,928 Semiconductor device and method of manufacturing semiconductor device
Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and...
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