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Patent # Description
US-9,922,927 Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
A first conductive element is disposed in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first...
US-9,922,926 Semiconductor device for transmitting electrical signals between two circuits
A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region...
US-9,922,925 Electronic component housing package, and electronic device comprising same
An electronic component housing package includes an insulating base including an upper surface, the insulating base including a first cut-out portion and a...
US-9,922,924 Interposer and semiconductor package
An interposer and a semiconductor package including the interposer are provided. The interposer includes a first dielectric layer, a conductive pillar, a...
US-9,922,923 Method of manufacturing wiring substrate and wiring substrate
To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a...
US-9,922,922 Microchip with cap layer for redistribution circuitry and method of manufacturing the same
A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over...
US-9,922,921 Tape wiring substrate, semiconductor package, and display apparatus including semiconductor package
A semiconductor package includes: a semiconductor chip including an effective chip region at a center of the semiconductor chip and in which pads connected to...
US-9,922,920 Semiconductor package and method for fabricating the same
A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface,...
US-9,922,919 Electronic package structure having insulated substrate with lands and conductive patterns
In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed...
US-9,922,918 Substrate for stacked module, stacked module, and method for manufacturing stacked module
A substrate for a stacked module includes a stacked insulator in which a plurality of insulator layers mainly composed of a thermoplastic resin are stacked, a...
US-9,922,917 Semiconductor package including substrates spaced by at least one electrical connecting element
The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an...
US-9,922,916 High density package interconnects
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die...
US-9,922,915 Bump-on-lead flip chip interconnection
A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the...
US-9,922,914 Plated terminals with routing interconnections semiconductor device
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
US-9,922,913 Plated terminals with routing interconnections semiconductor device
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
US-9,922,912 Package for die-bridge capacitor
In some examples, a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically...
US-9,922,911 Power module with double-sided cooling
Disclosed is a power module with double-sided cooling, comprising a semiconductor chip disposed between an upper substrate and a lower substrate; a first power...
US-9,922,910 Functionalized interface structure
An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating...
US-9,922,909 Display device
A display device is disclosed. In one aspect, the display device includes a substrate including a display area configured to display an image and a peripheral...
US-9,922,908 Semiconductor package having a leadframe with multi-level assembly pads
A leadframe (100) comprises a frame (101) of sheet metal in a first planar level, where the frame has metallic leads (110) and a first metallic pad (120)...
US-9,922,907 Electronic component, leadframe, and method for producing an electronic component
An electronic component, a leadframe, and a method for producing an electronic component are disclosed. In an embodiment, the electronic component includes a...
US-9,922,906 Electronic device and manufacturing method of electronic device
An electronic device includes first to third terminals and a clip. The clip includes first to third joint portions and a connection portion. The first to third...
US-9,922,905 Semiconductor device
A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and...
US-9,922,904 Semiconductor device including lead frames with downset
A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to...
US-9,922,903 Interconnect structure for package-on-package devices and a method of fabricating
An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon...
US-9,922,902 Semiconductor device and semiconductor package
A semiconductor device includes: a semiconductor element; a heat radiator body having a housing recess wherein a bottom surface of the housing recess is...
US-9,922,901 Heat conduction sheet, heat conduction sheet manufacture method, heat radiation member, and semiconductor device
A thermally conductive sheet including a sheet body that is a cured product of a thermally conductive resin composition including a binder resin and carbon...
US-9,922,900 Near-chip compliant layer for reducing perimeter stress during assembly process
A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which...
US-9,922,899 Method of manufacturing element chip and element chip
In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate...
US-9,922,898 Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
US-9,922,897 Method of manufacturing semiconductor package
A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a...
US-9,922,896 Info structure with copper pillar having reversed profile
A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first...
US-9,922,895 Package with tilted interface between device die and encapsulating material
A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of...
US-9,922,893 Semiconductor module
A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip...
US-9,922,892 Method and apparatus for bond-pad charging protection of transistor test structures
A method for preparing a non-reference transistor test structure having multiple terminals is disclosed. The method may include when an intended application of...
US-9,922,891 Film for semiconductor package, semiconductor package using film and display device including the same
A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor...
US-9,922,890 Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,922,889 Thermal processing method and thermal processing apparatus through light irradiation
A susceptor is preheated through light irradiation by a halogen lamp before the first semiconductor wafer of a lot as a processing target is transferred into a...
US-9,922,888 General four-port on-wafer high frequency de-embedding method
The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy,...
US-9,922,887 Wafer-scale testing of photonic integrated circuits using horizontal spot-size converters
Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.
US-9,922,886 Silicon-germanium FinFET device with controlled junction
Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a...
US-9,922,885 Semiconductor devices comprising nitrogen-doped gate dielectric
Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The...
US-9,922,884 Integrated circuit with replacement gate stacks and method of forming same
A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an...
US-9,922,883 Method for making strained semiconductor device and related methods
A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal...
US-9,922,882 Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided, and an epitaxial structure is formed on the...
US-9,922,881 Method for fabricating semiconductor device structure and product thereof
A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer,...
US-9,922,880 Method and apparatus of multi threshold voltage CMOS
A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a...
US-9,922,879 Integrated circuit devices
An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode...
US-9,922,878 Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing
A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an...
US-9,922,877 Connector structure and method for fabricating the same
A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive...
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