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Patent # Description
US-9,922,725 Integrated circuit defect detection and repair
In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in...
US-9,922,724 Methods of operating buffered multi-rank memory modules configured to selectively link rank control signals
A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer...
US-9,922,723 Volatile latch circuit with tamper resistant non-volatile latch backup
A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled...
US-9,922,722 Antifuse cell with capacitor and transistors
An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A...
US-9,922,721 Anti-fuse type one-time programmable memory cell array and method of operating the same
An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality...
US-9,922,720 Random fuse sensing
In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more...
US-9,922,719 Multi-VT sensing method by varying bit line voltage
Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell...
US-9,922,718 Flash command that reports a count of cell program failures
An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a...
US-9,922,717 Memory device to executed read operation using read target voltage
A memory device includes a first string including first and second memory cells, first and second select transistors, and a third select transistor between the...
US-9,922,716 Architecture for CMOS under array
Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise...
US-9,922,715 Non-volatile split gate memory device and a method of operating same
A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor...
US-9,922,714 Temperature dependent erase in non-volatile storage
Apparatuses and techniques are described for temperature dependent erase in non-volatile storage. In one aspect, select gate voltage magnitude depends on...
US-9,922,713 Memory device
Provided is an electronic device, such as a flash memory device and/or a write-once-read-once memory device, where the device has a polyoxometallate that is...
US-9,922,711 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material...
A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the...
US-9,922,710 Resistance variable memory apparatus and read circuit and method therefor
A resistance variable memory apparatus in accordance with an embodiment may include a memory cell array and a read circuit. The memory cell array may include a...
US-9,922,709 Memory hole bit line structures
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage...
US-9,922,708 Voltage controlling circuit
A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of Ovonic threshold switch (OTS) units. The second...
US-9,922,707 Semiconductor storage apparatus and memory system comprising memory cell holding data value of multiple bits
According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell...
US-9,922,706 Solid state storage device using state prediction method
A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is...
US-9,922,705 Reducing select gate injection disturb at the beginning of an erase operation
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase...
US-9,922,704 Programming memories with multi-level pass signal
Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a...
US-9,922,703 Multiport memory, memory macro and semiconductor device
A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals...
US-9,922,702 Apparatus for improving read stability
Described is an apparatus which comprises: a pass-gate; a sleep transistor configured as a diode-connected device controllable by the pass-gate; and a word-line...
US-9,922,701 Pre-charging bit lines through charge-sharing
In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first...
US-9,922,700 Memory read stability enhancement with short segmented bit line architecture
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first...
US-9,922,699 Adaptive diode sizing techniques for reducing memory power leakage
Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply...
US-9,922,698 Semiconductor memory device having a plurality of mosfets controlled to be in an active state or a standby state
A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells...
US-9,922,697 Memory device
A memory device may include: a plurality of cell mats arranged in a plurality of rows and columns; a plurality of first drivers, each first driver being...
US-9,922,696 Circuits and micro-architecture for a DRAM-based processing unit
A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing...
US-9,922,695 Apparatus and method for page copying within sections of a memory
An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination...
US-9,922,694 Apparatuses and methods for controlling refresh operations
An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit...
US-9,922,693 Adaptive refresh scheduling for memory
The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this...
US-9,922,692 Semiconductor device including refresh circuit for memory cell
To provide a semiconductor device which includes a novel refresh circuit in a memory including an oxide semiconductor film. As circuits which operate in a...
US-9,922,691 Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell...
US-9,922,690 Semiconductor devices having initialization circuits and semiconductor systems including the same
A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power...
US-9,922,689 Memory mapping
Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors....
US-9,922,688 Bitline sensing latch
A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using...
US-9,922,687 Memory system, semiconductor device and methods of operating the same
A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag...
US-9,922,686 Apparatuses and methods for performing intra-module databus inversion operations
Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module...
US-9,922,685 Semiconductor device and driving method thereof
A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which...
US-9,922,684 Memory device ultra-deep power-down mode exit control
A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply...
US-9,922,683 Power delivery circuitry
A memory device includes a memory system and an energy storage device including a capacitor. Additionally, the memory storage device includes power delivery...
US-9,922,682 Systems and methods for organizing video files
Electronic information defining visual content within video frames for playback may be accessed. The electronic information may be divided into electronic...
US-9,922,681 Techniques for adding interactive features to videos
Techniques are disclosed for adding interactive features to videos to enable users to create new media using a dynamic blend of motion and still imagery. The...
US-9,922,680 Method, an apparatus and a computer program product for processing image sequence tracks
There are disclosed various methods, apparatuses and computer program products for video encoding. According to an embodiment, an encoding method comprises...
US-9,922,679 Slow motion video playback method for computing devices with touch interfaces
Disclosed is a system and method for controlling the playback speed, and user experience, of watching slow motion video content on a touch sensitive computing...
US-9,922,678 Error correction for storage devices
Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units...
US-9,922,677 Library device, cartridge jump-out preventing mechanism and method
A library device includes: a housing for accommodating a magazine to be able to be put in and out, wherein the magazine has slots for accommodating recording...
US-9,922,676 Data storage device gradually decreasing laser power after write operation
A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a laser configured to heat the disk while writing data to...
US-9,922,675 Optical disk drive with multiple optical pick-up heads
An optical disk drive with multiple optical pick-up heads is provided. The optical disk drive includes an upper cover, a base, a first carrier member, a second...
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