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Patent # Description
US-9,947,788 Device with diffusion blocking layer in source/drain region
A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a...
US-9,947,787 Devices and methods for a power transistor having a schottky or schottky-like contact
Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are...
US-9,947,786 Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for...
The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples...
US-9,947,785 Junction field effect transistor and manufacturing method therefor
The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the...
US-9,947,784 High voltage lateral extended drain MOS transistor with improved drift layer contact
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region...
US-9,947,783 P-channel DEMOS device
A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width...
US-9,947,782 Semiconductor device and method for manufacturing same
A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon...
US-9,947,781 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride...
US-9,947,780 High electron mobility transistor (HEMT) and method of fabrication
Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and...
US-9,947,779 Power MOSFET having lateral channel, vertical current path, and P-region under gate for increasing breakdown...
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type...
US-9,947,778 Lateral bipolar junction transistor with controlled junction
A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and...
US-9,947,777 Semiconductor device and method for manufacturing semiconductor device
Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide...
US-9,947,776 Method for manufacturing semiconductor device including memory cell of nonvolatile memory, capacitance element,...
To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an...
US-9,947,775 Replacement III-V or germanium nanowires by unilateral confined epitaxial growth
A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium...
US-9,947,774 Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid...
A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor...
US-9,947,773 Semiconductor arrangement with substrate isolation
One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel,...
US-9,947,772 SOI FinFET transistor with strained channel
Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency...
US-9,947,771 Thin film transistor and method of fabricating the same
A method of fabricating a thin film transistor includes forming a substrate having first and second regions, a semiconductor layer pattern formed in the first...
US-9,947,770 Self-aligned trench MOSFET and method of manufacture
A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions...
US-9,947,769 Multiple-layer spacers for field-effect transistors
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor....
US-9,947,768 Method for forming spacers for a transistor gate
A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method...
US-9,947,767 Self-limited inner spacer formation for gate-all-around field effect transistors
A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel...
US-9,947,766 Semiconductor device and fabricating method thereof
A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The...
US-9,947,765 Dummy gate placement methodology to enhance integrated circuit performance
A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an...
US-9,947,764 Dummy gate structure and methods thereof
A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation...
US-9,947,763 FinFET with reduced capacitance
A method including depositing a gap fill material on top of a conformal dummy gate oxide above and in between a plurality of fins, forming one or more openings...
US-9,947,762 MOS devices with mask layers and methods for forming the same
A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are...
US-9,947,761 Production method for semiconductor device
A method for producing a semiconductor device includes an implantation step of performing proton implantation from a rear surface of a semiconductor substrate...
US-9,947,760 Method for manufacturing an emitter for high-speed heterojunction bipolar transistors
A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench...
US-9,947,759 Semiconductor device having milti-height structure and method of manufacturing the same
A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure...
US-9,947,758 Forming silicide regions and resulting MOS devices
A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a...
US-9,947,757 Display device, array substrate, and thin film transistor
A method for manufacturing the thin film transistor, including: forming a gate, an active layer and a gate insulating layer disposed between the gate and the...
US-9,947,756 Semiconductor device and manufacturing method thereof
In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An...
US-9,947,755 III-V MOSFET with self-aligned diffusion barrier
A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source...
US-9,947,754 Manufacturing method of array substrate and LCD panel
The invention provides a manufacturing method of array substrate, wherein a light-shielding layer is disposed on the semiconductor layer, the light-shielding...
US-9,947,753 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor....
US-9,947,752 Semiconductor device having protection film with recess
A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a...
US-9,947,751 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided...
US-9,947,750 Silicon carbide semiconductor switching device and method of manufacturing silicon carbide semiconductor...
A silicon carbide semiconductor switching device having a planar metal oxide semiconductor insulated gate structure. The silicon carbide semiconductor switching...
US-9,947,749 Thin film compositions and methods
Certain embodiments of the present invention include a versatile and scalable process, "patterned regrowth," that allows for the spatially controlled synthesis...
US-9,947,748 Dielectric isolated SiGe fin on bulk substrate
A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric...
US-9,947,747 Fully depleted silicon-on-insulator device formation
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described....
US-9,947,745 Substrate structure with embedded layer for post-processing silicon handle elimination
The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure...
US-9,947,744 Nanowire semiconductor device including lateral-etch barrier region
A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier...
US-9,947,743 Structures and methods for long-channel devices in nanosheet technology
Techniques for providing supporting structures for suspended nanosheets/wires in long-channel devices are provided. In one aspect, a method of forming a device...
US-9,947,742 Power semiconductor device
A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the...
US-9,947,741 Field-effect semiconductor device having pillar regions of different conductivity type arranged in an active area
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are...
US-9,947,740 On-chip MIM capacitor
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate...
US-9,947,739 Display device array substrate without frame
An array substrate and a display device are provided. The array substrate includes: a gate driving circuit, no pixel electrode layer being provided on a...
US-9,947,738 Display panel including multilayer wiring and member for reducing probability of power line mis-pressing during...
A display panel including: a substrate; a multi-layer wiring layer disposed over the substrate and including a first power line and a second power line; organic...
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