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Patent # Description
US-9,947,687 Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two...
US-9,947,686 Semiconductor device including a stack having a sidewall with recessed and protruding portions
A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers...
US-9,947,685 3D non-volatile memory array utilizing metal ion source
According to one embodiment, a semiconductor memory device includes a semiconductor layer, a plurality of conductive layers, a plurality of insulating layers,...
US-9,947,684 Three-dimensional semiconductor device
A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure...
US-9,947,683 Three-dimensional semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second...
US-9,947,682 Three dimensional non-volatile memory with separate source lines
A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below...
US-9,947,681 Semiconductor device and method for manufacturing same
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with...
US-9,947,680 Semiconductor memory device
A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first...
US-9,947,679 Method of manufacturing semiconductor device with separately formed insulating films in main circuit and memory...
An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate...
US-9,947,678 Wing-type projection between neighboring access transistors in memory devices
A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective...
US-9,947,677 High-density EEPROM arrays having parallel-connected common-floating-gate NFET and PFET as memory cell
A memory array includes an N.times.M array of memory cells, each memory cell having a first transistor connected to a first terminal and a second transistor...
US-9,947,676 NVM memory HKMG integration technology
The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high...
US-9,947,675 Mask-programmable ROM using a vertical FET integration process
A mask programmable read-only memory (PROM) cell is provided utilizing a vertical transistor processing flow. PROM programming is performed during the...
US-9,947,674 Static random-access memory (SRAM) cell array
A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein...
US-9,947,673 Semiconductor memory device
The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a...
US-9,947,672 Semiconductor devices including a dummy gate structure on a fin
Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The...
US-9,947,671 Semiconductor device including transistors having different threshold voltages
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a...
US-9,947,670 Semiconductor device
A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor...
US-9,947,669 Dynamic random access memory and method of manufacturing the same
A dynamic random access memory (DRAM) includes a substrate, a plurality of isolation structures, a plurality of conductive structure sets, a plurality of...
US-9,947,668 Semiconductor devices and methods of forming the same
Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral...
US-9,947,667 Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the...
A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a...
US-9,947,666 Semiconductor device structures including buried digit lines and related methods
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material...
US-9,947,665 Semiconductor structure having dielectric layer and conductive strip
A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second...
US-9,947,664 Semiconductor device and method of forming the semiconductor device
A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the...
US-9,947,663 FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET
A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the...
US-9,947,662 CMOS circuits suitable for low noise RF applications
A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type...
US-9,947,661 Semiconductor device and method of manufacturing the same
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from...
US-9,947,660 Two dimension material fin sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls....
US-9,947,659 Fin field-effect transistor gated diode
The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of...
US-9,947,658 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the...
US-9,947,657 Semiconductor device and a method for fabricating the same
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region...
US-9,947,656 Integrated circuit devices including fin active areas with different shapes
An integrated circuit device can include a substrate having a first area and a second area and a pair of first fin-shaped active areas each having a first shape...
US-9,947,655 3D bonded semiconductor structure with an embedded capacitor
A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure...
US-9,947,654 Electronic device including a transistor and a field electrode
In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain...
US-9,947,653 High-voltage semiconductor devices
A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the...
US-9,947,652 Display device
A structure of connecting a panel driver to a side of a display panel and an electrostatic discharge (ESD) structure are discussed. The display device comprises...
US-9,947,651 Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal
A semiconductor integrated circuit device with a "PAD on I/O cell" structure in which a pad lead part is disposed almost in the center of an I/O part so as to...
US-9,947,650 Device for protection against electrostatic discharges with a distributed trigger circuit
An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a...
US-9,947,649 Large area electrostatic dischage for vertical transistor structures
A semiconductor structure including an electrostatic discharge (ESD) diode with an increased junction area and a vertical field effect transistor (FET) formed...
US-9,947,648 Semiconductor device including a diode at least partly arranged in a trench
A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including...
US-9,947,647 Method and system for over-voltage protection using transient voltage suppression devices
A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device...
US-9,947,646 Method and structure for semiconductor mid-end-of-line (MEOL) process
A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source,...
US-9,947,644 Semiconductor package
A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package...
US-9,947,643 Inverted optical device
Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The...
US-9,947,642 Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located...
US-9,947,641 Wire bond support structure and microelectronic package including wire bonds therefrom
A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least...
US-9,947,640 Wafer, package structure and method of manufacturing the same
The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a...
US-9,947,639 Semiconductor module
A semiconductor module (10A) according to one embodiment includes a plurality of first and second transistor chips (hereinafter, first and second transistors)...
US-9,947,638 Device and method for permanent bonding
A method and corresponding device for permanent bonding of a first layer of a first substrate to a second layer of a second substrate on a bond interface,...
US-9,947,637 System and method for clamping wafers together in alignment using pressure
A system and method for clamping wafers together in alignment using pressure. The system and method involves holding a first wafer and a second wafer together...
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