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Patent # Description
US-9,947,636 Method for making semiconductor device with lead frame made from top and bottom components and related devices
A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead...
US-9,947,635 Semiconductor package, interposer and semiconductor process for manufacturing the same
A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at...
US-9,947,634 Robust mezzanine BGA connector
A ball grid array (BGA) connector including an outer housing, an insert mounted within the outer housing having a first side and a second side, and a plurality...
US-9,947,633 Deformable conductive contacts
Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a second...
US-9,947,632 Semiconductor device and method of making a semiconductor device
A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on...
US-9,947,631 Surface finishes for interconnection pads in microelectronic structures
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus,...
US-9,947,630 Package with solder regions aligned to recesses
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer...
US-9,947,629 Method of forming contact holes in a fan out package
Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical...
US-9,947,628 High frequency semiconductor amplifier
A high frequency semiconductor amplifier includes an input circuit, a first semiconductor element, first bonding wires, an interstage circuit, second bonding...
US-9,947,627 Guard ring structure and method for forming the same
A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second...
US-9,947,626 Eliminate sawing-induced peeling through forming trenches
A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top...
US-9,947,625 Wiring board with embedded component and integrated stiffener and method of making the same
A wiring board with embedded component and integrated stiffener is characterized in that an embedded semiconductor device, a first routing circuitry, an...
US-9,947,624 Semiconductor package assembly with through silicon via interconnect
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package...
US-9,947,623 Semiconductor device comprising a conductive pad on a protruding-through electrode
A semiconductor device. For example and without limitation, various aspects of the present disclosure provide a semiconductor device that comprises a...
US-9,947,622 Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low...
An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting...
US-9,947,621 Structure and method to reduce copper loss during metal cap formation
A copper or copper alloy is formed in a reflow enhancement layer lined opening present in an interconnect dielectric material layer. A ruthenium (Ru) or osmium...
US-9,947,620 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a wiring layer, an insulating layer, a contact plug, a pillar and a pad. The wiring layer is...
US-9,947,619 Coupling structures for signal communication and method of making same
Techniques and mechanism to provide signal communication with vias variously extending in a substrate. In an embodiment, a first capacitor and a second...
US-9,947,618 Microelectronic components with features wrapping around protrusions of conductive vias protruding from...
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A,...
US-9,947,617 Series MIM structures
The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has...
US-9,947,616 High power MMIC devices having bypassed gate transistors
Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The...
US-9,947,615 Electronic circuit and camera
An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for...
US-9,947,614 Packaged semiconductor device having bent leads and method for forming
A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated...
US-9,947,613 Power semiconductor device and method for manufacturing the same
A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first...
US-9,947,612 Semiconductor device with frame having arms and related methods
A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly...
US-9,947,611 Through hole arrays for flexible layer interconnects
Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical...
US-9,947,610 Semiconductor structure and method for manufacturing the same
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a buffer layer, at least one recess, and at least one conductor. The...
US-9,947,609 Integrated circuit stack
In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an...
US-9,947,608 Method of manufacture for a semiconductor device
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal...
US-9,947,607 Inverter
An inverter includes: an inverter circuit including: a power semiconductor module; and an inverter circuit module including a passive component; a cooler...
US-9,947,606 Semiconductor device including electromagnetic absorption and shielding
A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding...
US-9,947,605 Flip chip cavity package
A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is...
US-9,947,604 Epoxy resin composition, semiconductor sealing agent, and semiconductor device
An epoxy resin composition includes: (A) epoxy resin; (B) a curing agent; (C) 0.1 to 10 mass % of silica filler with an average particle size of 10 nm or more...
US-9,947,603 Lid attach optimization to limit electronic package warpage
An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and...
US-9,947,602 IC structure integrity sensor having interdigitated conductive elements
A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a...
US-9,947,601 Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,947,600 Semiconductor structure having a test structure formed in a group III nitride layer
In an embodiment, a semiconductor structure includes a support substrate comprising a surface adapted to support epitaxial growth of a Group III nitride, one or...
US-9,947,599 Method for PECVD overlay improvement
The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic...
US-9,947,598 Determining crackstop strength of integrated circuit assembly at the wafer level
A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure...
US-9,947,597 Defectivity metrology during DSA patterning
The described embodiments include performing a curing process for selective treatment, or hardening, of PS regions in PS-b-PMMA block copolymer DSA films prior...
US-9,947,596 Range-based real-time scanning electron microscope non-visual binner
A technique to identify non-visual defects, such as SEM non-visual defects (SNVs), includes generating an image of a layer of a wafer, evaluating at least one...
US-9,947,595 Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack...
US-9,947,594 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack...
US-9,947,593 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
US-9,947,592 FinFET devices and methods of forming the same
FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The...
US-9,947,591 Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices
A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate...
US-9,947,590 Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a...
At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature....
US-9,947,589 Methods of forming a gate contact for a transistor above an active region and the resulting device
A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent...
US-9,947,588 Method for manufacturing fins
A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is...
US-9,947,587 Method of forming fin structure of semiconductor device
A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed...
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