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Patent # Description
US-9,947,586 Tunneling fin type field effect transistor with epitaxial source and drain regions
A method of forming semiconductor devices may begin with forming gate structures over fin structures on sidewalls of at least two mandrels. The mandrels are...
US-9,947,585 Multi-gate transistor with variably sized fin
An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a...
US-9,947,584 Systems and methods for controlling release of transferable semiconductor structures
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
US-9,947,583 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the...
US-9,947,582 Processes for preventing oxidation of metal thin films
Processes are provided herein for protecting metal thin films from oxidation when exposed to an oxidizing environment, such as the ambient atmosphere. The...
US-9,947,581 Method of forming a copper based interconnect structure
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
US-9,947,580 Interconnect structures with enhanced electromigration resistance
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction...
US-9,947,579 Copper interconnect structure with manganese oxide barrier layer
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
US-9,947,578 Methods for forming low-resistance contacts through integrated process flow systems
Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing...
US-9,947,577 Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
A method of forming an integrated circuit that includes providing a substrate, a metal layer over the substrate, and a first dielectric layer over the metal...
US-9,947,576 UV-assisted material injection into porous films
Methods are described for reducing shrinkage experienced by porous films on a patterned substrate. The film may be a silicon-and-hydrogen-containing layer which...
US-9,947,575 Semiconductor device and semiconductor device fabrication method
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating...
US-9,947,574 Semiconductor device
A semiconductor device according to an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first...
US-9,947,573 Lateral PiN diodes and schottky diodes
Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The...
US-9,947,572 Substrate processing apparatus
In a substrate processing apparatus, a shield plate includes a first chucking magnetic material (441). The shield plate is moved up and down by a chamber...
US-9,947,571 Processing apparatus, nozzle, and dicing apparatus
A processing apparatus of an embodiment includes a stage that can have a sample placed thereon, a rotation mechanism that rotates the stage, a nozzle that...
US-9,947,570 Handler bonding and debonding for semiconductor dies
Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive...
US-9,947,569 Carrier tape and pack
A carrier tape is provided from which LEDs can be easily picked up. A carrier tape for accommodating an LED includes a sheet defining recessed embossed portions...
US-9,947,568 Peeling method, semiconductor device, and peeling apparatus
To improve peelability, yield in a peeling step, and yield in manufacturing a flexible device. A peeling method is employed which includes a first step of...
US-9,947,567 Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding
A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an...
US-9,947,566 Substrate angle alignment device, substrate angle alignment method, and substrate transfer method
A substrate angle alignment device includes a plurality of holding sections which hold a plurality of substrates, respectively in such a manner that the...
US-9,947,565 Workpiece stocker with circular configuration
An improved stocker configuration for storing workpieces in a fabrication facility is disclosed, employing workpiece compartments arranged stationarily around a...
US-9,947,564 Conveyance base and conveyance system
Provided is a conveyance system that adjusts the position of a conveyed substrate, prevents damage resulting from the heat of another apparatus in a conveyance...
US-9,947,563 Wafer container with air-tight device
A wafer container is provided. The wafer container includes a housing, a door and an air-tight device. The housing has a room with an opening formed therein,...
US-9,947,562 Method and apparatus for processing semiconductor work pieces
A processing apparatus for semiconductor work pieces and related methodology is disclosed and which includes a processing chamber having an internal cavity, and...
US-9,947,561 Semiconductor encapsulation system comprising a vacuum pump and a reservoir pump
A semiconductor encapsulation apparatus for encapsulating a semiconductor device on a substrate, the apparatus comprising a mold comprising a cavity pressure...
US-9,947,560 Integrated circuit package, and methods and tools for fabricating the same
An integrated circuit (IC) package, assembly tool and method for assembling an IC package are described herein. In a first example, an IC package is provided...
US-9,947,559 Thermal management of edge ring in semiconductor processing
Apparatus for processing semiconductors are provided herein. In some embodiments, an apparatus for processing a substrate may include: a first ring disposed...
US-9,947,558 Method for conditioning silicon part
A method for conditioning and cleaning a silicon part is provided. The silicon part is heated to a temperature of at least 300.degree. C. in the presence of...
US-9,947,557 Semiconductor processing system having multiple decoupled plasma sources
A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate...
US-9,947,556 Substrate cleaning apparatus, substrate cleaning method, and storage medium
There are provided first and second cleaning members which are configured to clean a central zone in a rear surface of a wafer when the wafer held by an...
US-9,947,555 Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
In one embodiment, a semiconductor manufacturing apparatus includes a wafer retaining module configured to retain a wafer by a chuck pin and to rotate the...
US-9,947,554 Support substrate and a method of manufacturing a semiconductor package using the same
A support substrate, a method of manufacturing a semiconductor package, and a semiconductor package, the support substrate including a first plate; a second...
US-9,947,553 Manufacturing method of semiconductor device and semiconductor device
The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. The method comprises: Preparing a semiconductor...
US-9,947,552 Structure and formation method of chip package with fan-out structure
Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and...
US-9,947,551 Chip package structure and manufacturing method thereof
A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition...
US-9,947,550 Film forming method and method of manufacturing thin film transistor
Provided is a film forming method to minimize decreases in the electrical resistance of an oxide semiconductor film even when a fluorinated silicon nitride film...
US-9,947,549 Cobalt-containing material removal
Methods are described herein for etching cobalt films which are difficult to volatize. The methods include exposing a cobalt film to a bromine or ...
US-9,947,547 Environmentally green process and composition for cobalt wet etch
An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or...
US-9,947,546 Semiconductor integrated circuit device with a surface and method of manufacturing the same
A semiconductor integrated circuit device and a method of manufacturing the same are disclosed. A semiconductor wafer having a surface step is prepared. A first...
US-9,947,545 Methods for gate formation in circuit structures
Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in...
US-9,947,544 Method of manufacturing semiconductor device including forming protective film within recess in substrate
An n-type layer (3) is formed by implanting an n-type impurity in a back surface of a Si substrate (1). A recess (4) is formed in the back surface of the Si...
US-9,947,543 Semiconductor memory device and manufacturing method thereof
The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a...
US-9,947,541 Method of forming spacers for a gate of a transistor
A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a...
US-9,947,540 Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby
Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A...
US-9,947,539 Plasma poisoning to enable selective deposition
Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state...
US-9,947,538 Semiconductor device manufacturing method including heat treatment
A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor structure that comprises a substrate and a first...
US-9,947,537 Method of forming a P-type ohmic contact in group-III nitride semiconductors
There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700.degree. C.-1150.degree. C., a good ohmic contact cannot...
US-9,947,536 Semiconductor power device and method for producing same
A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first...
US-9,947,535 Trench formation using horn shaped spacer
A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than...
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