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Patent # Description
US-9,966,396 High dynamic range image sensor with reduced sensitivity to high intensity light
An image sensor includes first and second pluralities of photodiodes interspersed among each other in a semiconductor substrate. Incident light is to be...
US-9,966,395 Solid-state image sensor and method of manufacturing the same
A solid-state image sensor is provided. The sensor includes a first transistor including a first diffusion region, a second transistor including a second...
US-9,966,394 Light sensing device and fabricating method thereof
A light sensing device includes a substrate, a semiconductor device layer, a metal and insulation material stacked structure, and a light absorption layer. The...
US-9,966,393 Array substrate and method of fabricating the same
A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate...
US-9,966,392 Laser annealing apparatus and method of manufacturing display apparatus by using the same
A laser annealing apparatus includes: a substrate supporting unit which supports a substrate; a laser beam irradiating unit which irradiates a line laser beam...
US-9,966,391 Backplane for display apparatus
A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a...
US-9,966,390 Display device
A display device includes first to fifth insulating films, first to third conductive films, semiconductor film, a planarization layer, an organic resin film, a...
US-9,966,389 Array substrate and manufacturing method thereof and display device
This invention provides an array substrate, a manufacturing method thereof and a display device, the array substrate comprises a common electrode line, a thin...
US-9,966,387 Strain release in pFET regions
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric...
US-9,966,386 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A...
US-9,966,385 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, columnar portions, and first and second interconnection...
US-9,966,384 Methods of manufacturing a semiconductor device with non-overlapping slits in-between memory blocks
A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first...
US-9,966,383 Semiconductor structure and manufacturing method thereof
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory...
US-9,966,382 Semiconductor structure and method for fabricating the same
A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor...
US-9,966,381 Semiconductor memory device and method for manufacturing the same
A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film...
US-9,966,380 Select gate self-aligned patterning in split-gate flash memory cell
A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A...
US-9,966,379 Semiconductor device, related manufacturing method, and related electronic device
A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the...
US-9,966,378 Integrated circuit structure
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also...
US-9,966,377 Semiconductor devices including fin-shaped active patterns in different conductivity type regions
A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern...
US-9,966,376 Semiconductor devices and inverter having the same
Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device...
US-9,966,375 Semiconductor device
A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The...
US-9,966,374 Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween
A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer...
US-9,966,373 MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal...
Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions...
US-9,966,372 Semiconductor device and method of manufacturing semiconductor device having parallel contact holes between...
A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a...
US-9,966,371 Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first...
US-9,966,370 Method for producing optoelectronic semiconductor devices
A method for producing a plurality of optoelectronic semiconductor devices is provided. A number of semiconductor chips are fastened on an auxiliary support....
US-9,966,369 Light emitting device package
A light emitting device package includes a cell array including a plurality of semiconductor light emitting units, and having a first surface and a second...
US-9,966,368 Semiconductor devices for integration with light emitting chips and modules thereof
A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost...
US-9,966,367 Light emitting device
A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a...
US-9,966,366 Lighting device
A lighting device includes a plurality of light-emitting diodes including a first light-emitting diode with a non-rectangular shape in a top view, a submount to...
US-9,966,365 Display device and fabricating method
In accordance with various embodiments, the disclosed subject matter provides a display device and a related fabricating method. In some embodiments, the...
US-9,966,364 Semiconductor package and method for fabricating the same
A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the...
US-9,966,363 Semiconductor apparatus and method for preparing the same
A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted...
US-9,966,361 Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness...
US-9,966,360 Semiconductor package and manufacturing method thereof
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a...
US-9,966,359 Semiconductor package embedded with a plurality of chips
A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip...
US-9,966,358 Chip package
A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on...
US-9,966,357 Pick-and-place tool for packaging process
A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method...
US-9,966,356 Laser-induced forming and transfer of shaped metallic interconnects
A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using...
US-9,966,355 Aluminum coated copper bond wire and method of making the same
A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over...
US-9,966,353 Power module substrate, method of producing same, and power module
An elongated trench (35) is formed so as to connect the Ag layer (32) and the exposed part of the circuit layer stretching out around the Ag layer (32). The...
US-9,966,351 Grid array connection device and method
A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as...
US-9,966,350 Wafer-level package device
Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five...
US-9,966,349 Semiconductor memory device structure
A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of...
US-9,966,348 Method for processing an electronic component and an electronic component
According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a...
US-9,966,347 Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package...
US-9,966,346 Bump structure and method of forming same
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically...
US-9,966,345 Protective barrier for integrated circuit packages housing a voltage regulator and a load
An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core...
US-9,966,344 Semiconductor device with separated main terminals
A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor...
US-9,966,343 Electronic circuit package
Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the...
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