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Patent # Description
US-9,997,537 Semiconductor devices including gate insulation layers on channel materials and methods of forming the same
Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device...
US-9,997,536 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar section and an interconnection section. The stacked...
US-9,997,535 Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a...
US-9,997,533 Semiconductor device and method for manufacturing same
According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of...
US-9,997,532 Semiconductor device and method of fabricating the same
A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings,...
US-9,997,531 Semiconductor memory device
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: an inter-layer insulating layer and a...
US-9,997,530 Three-dimensional semiconductor memory device and method of fabricating the same
A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit...
US-9,997,529 Semiconductor memory device
A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third...
US-9,997,528 Complimentary SONOS integration into CMOS flow
Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM)...
US-9,997,527 Method for manufacturing embedded non-volatile memory
In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A...
US-9,997,526 Semiconductor device and method for manufacturing same
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with...
US-9,997,525 Semiconductor devices and methods of fabricating the same
A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate...
US-9,997,524 Semiconductor memory device and manufacturing method thereof
A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and...
US-9,997,523 Static random access memory (SRAM) cells including vertical channel transistors and methods of forming the same
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down...
US-9,997,522 Method for fabricating a local interconnect in a semiconductor device
A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate...
US-9,997,521 Semiconductor devices
Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a...
US-9,997,520 Semiconductor device structure with capacitor and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive...
US-9,997,519 Dual channel structures with multiple threshold voltages
A method of forming a semiconductor structure includes depositing a first work function metal layer in nanosheet channel stacks for first and second CMOS...
US-9,997,518 Low resistive electrode for an extendable high-k metal gate stack
In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate;...
US-9,997,517 Power semiconductor device having fully depleted channel regions
A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load...
US-9,997,516 Semiconductor device and power amplifier circuit
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main...
US-9,997,515 Semiconductor devices with trench gate structures in a semiconductor body with hexagonal crystal lattice
A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted...
US-9,997,514 Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit
Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver...
US-9,997,513 Package including a plurality of stacked semiconductor devices having area efficient ESD protection
A multi-chip device can include stacked semiconductor devices including a top and bottom semiconductor device. The top semiconductor device can include a first...
US-9,997,512 Electronic device for ESD protection
An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is...
US-9,997,511 ESD protection circuit with plural avalanche diodes
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and...
US-9,997,510 Semiconductor device layout structure
The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well...
US-9,997,509 Electrostatic discharge (ESD) protection circuit
Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection...
US-9,997,508 Integrated photo detector, method of making the same
An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in...
US-9,997,507 Semiconductor assembly and method of manufacture
A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride...
US-9,997,506 Assembly of wafer stacks
A method of forming a wafer stack includes providing a sub-stack comprising a first wafer and a second wafer. The sub-stack includes a first thermally-curable...
US-9,997,505 Lighting device, backlight module and illumination module
Various examples of a lighting device, backlight module and illumination module are described. A lighting device includes a carrier component, an LED chip, a...
US-9,997,504 Electronic device module and method of manufacturing the same
In one general aspect, an electronic device module includes a first board, a first device mounted on a first surface of the first board, a second board disposed...
US-9,997,503 Composite substrate and light emitting device
The composite substrate includes: a lead frame including one or more pairs of support leads, each of the one or more pairs of support leads including a first...
US-9,997,502 Component arrangement determination method
There is provided a component arrangement determination method, in a component mounting apparatus including a plurality of component supply units for supplying...
US-9,997,501 Micro-transfer-printed light-emitting diode device
A compound light-emitting diode (LED) device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor substrate....
US-9,997,500 Common-source packaging structure
A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a...
US-9,997,499 Semiconductor device and method of manufacturing the same
Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a...
US-9,997,498 Semiconductor package assembly
In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die,...
US-9,997,497 Through silicon via structure
A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a...
US-9,997,496 Semiconductor integrated circuit
A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the...
US-9,997,495 Non-contacting inductive interconnects
A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first...
US-9,997,494 Three-dimensional silicon structure for integrated circuits and cooling thereof
Embodiments of a three-dimensional silicon structure for integrated circuits and cooling thereof are described. In one aspect, a device includes a silicon...
US-9,997,493 Flexible-substrate-based three-dimensional packaging structure and method
The present invention mainly relates to a 3-D packaging structure based on a flexible substrate and a method for manufacturing the same; the method comprises:...
US-9,997,492 Optically-masked microelectronic packages and methods for the fabrication thereof
Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes...
US-9,997,491 Method of determining curing conditions, method of producing circuit device, and circuit device
A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an...
US-9,997,490 Window clamp
A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame...
US-9,997,489 Coated bond wires for die packages and methods of manufacturing said coated bond wires
A bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings....
US-9,997,488 Copper-based alloy wire and methods for manufaturing the same
A copper-based alloy wire made of a material selected from the group consisting of a copper-gold alloy, a copper-palladium alloy and a copper-gold-palladium...
US-9,997,487 Display device with improved anisotropic conductive film
A display device includes: a first substrate; a wire portion disposed on the first substrate; a pad portion connected with the wire portion; a printed circuit...
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