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| Patent # | Description |
|---|---|
| US-9,997,435 |
Compliant pin fin heat sink and methods A heat sink includes a plurality of layers being disposed substantially parallel with a surface of a heat source. The layers include a plurality of pin portions... |
| US-9,997,434 |
Substrate sprayer An example device in accordance with an aspect of the present disclosure includes a substrate that may be disposed in a housing. The substrate includes a... |
| US-9,997,433 |
Heat dissipating device and manufacturing method of heat dissipating
device A heat dissipating device includes a heat dissipating module, a heat pipe, and an injection molded member formed by molding and solidifying. The heat pipe has a... |
| US-9,997,432 |
Semiconductor device and electronic component using the same A semiconductor device includes: a heat spreader; a semiconductor element on the heat spreader; and a connection member arranged between the heat spreader and... |
| US-9,997,431 |
Electronic device provided with a thermal dissipation member An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support... |
| US-9,997,430 |
Heat dissipation structure of semiconductor device A heat dissipation structure of a semiconductor device with excellent heat dissipation applicable to surface-mount thin semiconductor devices is provided, and... |
| US-9,997,429 |
Trench-type heat sink structure applicable to semiconductor device The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first... |
| US-9,997,428 |
Via structures for thermal dissipation An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in... |
| US-9,997,427 |
Display panel with dam structure A display panel includes a first inorganic capping layer (INOCL) in a non-displaying area (A.sub.ND) of a substrate, a first electrode in the A.sub.ND formed on... |
| US-9,997,426 |
Thermally enhanced semiconductor package with thermal additive and process
for making the same The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a... |
| US-9,997,425 |
Layered benzocyclobutene interconnected circuit and method of
manufacturing same An integrated circuit includes stacked benzocyclobutene layers and a circuit geometry comprising conductive electric traces and interconnects on and/or... |
| US-9,997,424 |
Method of forming a temporary test structure for device fabrication A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during... |
| US-9,997,423 |
Semiconductor wafer and method of concurrently testing circuits formed
thereon A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads... |
| US-9,997,422 |
Systems and methods for frequency modulation of radiofrequency power
supply for controlling plasma instability A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode.... |
| US-9,997,421 |
Top contact resistance measurement in vertical FETS A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction... |
| US-9,997,420 |
Method and/or system for chemical mechanical planarization (CMP) One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector,... |
| US-9,997,419 |
Confined eptaxial growth for continued pitch scaling A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on... |
| US-9,997,418 |
Dual liner silicide A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate... |
| US-9,997,417 |
Semiconductor device structure with gate spacer having protruding bottom
portion and method for forming the same A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack... |
| US-9,997,416 |
Low resistance dual liner contacts for fin field-effect transistors
(FinFETs) A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first... |
| US-9,997,415 |
Formation of nickel silicon and nickel germanium structure at staggered
times A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material... |
| US-9,997,414 |
Ge/SiGe-channel and III-V-channel transistors on the same die Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of... |
| US-9,997,413 |
Stacked vertical devices A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first... |
| US-9,997,412 |
Methods of manufacturing semiconductor devices A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other... |
| US-9,997,411 |
Formation of metal resistor and e-fuse Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second... |
| US-9,997,410 |
Methods for forming the isolation structure of the semiconductor device
and semiconductor devices A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area... |
| US-9,997,409 |
Fabricating contacts of a CMOS structure The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a... |
| US-9,997,408 |
Method of optimizing wire RC for device performance and reliability A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is... |
| US-9,997,407 |
Voidless contact metal structures Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that... |
| US-9,997,406 |
Columnar interconnects and method of making them Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric... |
| US-9,997,405 |
Feature fill with nucleation inhibition Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some... |
| US-9,997,404 |
Method of forming an interconnect structure for a semiconductor device Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer... |
| US-9,997,403 |
Metal layer tip to tip short Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An... |
| US-9,997,402 |
Method of manufacturing a wiring structure on a self-forming barrier
pattern In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The... |
| US-9,997,401 |
Method for forming a via profile of interconnect structure of
semiconductor device structure A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric... |
| US-9,997,400 |
Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection... |
| US-9,997,399 |
Method for transferring semiconductor structure A method for transferring a semiconductor structure is provided. The method includes: coating an adhesive layer onto a carrier substrate; disposing the... |
| US-9,997,398 |
Methods of forming one or more covered voids in a semiconductor substrate Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for... |
| US-9,997,397 |
Semiconductor structure and manufacturing method thereof A semiconductor structure includes a substrate, at least one first epitaxial layer, and at least one second epitaxial layer. The substrate has a plurality of... |
| US-9,997,396 |
Deep trench isolation structure and method for improved product yield A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench... |
| US-9,997,395 |
Fabrication method of a stack of electronic devices This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b)... |
| US-9,997,394 |
Method for transferring a thin layer with supply of heat energy to a
fragile zone via an inductive layer A method of transferring a thin layer from a first substrate to a second substrate with different coefficients of thermal expansion, including: providing at... |
| US-9,997,393 |
Methods for fabricating integrated circuits including substrate contacts Methods for fabricating integrated circuits are provided. In one example, a method includes depositing an ILD layer overlying a SOI substrate including a device... |
| US-9,997,392 |
Wafer processing method In a wafer processing method, the back side of a wafer is attached to an adhesive tape supported at its peripheral portion by an annular frame having an inside... |
| US-9,997,391 |
Lift off process for chip scale package solid state devices on engineered
substrate A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an... |
| US-9,997,390 |
Semiconductor manufacturing method and laminated body A semiconductor manufacturing method according to a present embodiment includes forming a supporter on a second surface of a semiconductor substrate opposite to... |
| US-9,997,389 |
Bipolar mobile electrostatic carriers for wafer processing In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode... |
| US-9,997,388 |
Substrate container with purge ports A breather assembly mounted to the purge port of a substrate carrier for coupling with a tool port. In various embodiments, the breather assembly comprises a... |
| US-9,997,387 |
Purge device, purge system, purge method, and control method in purge
system A purge device configured to purge the inside of a storage container storing a product with purge gas includes a plurality of placing units, each configured to... |
| US-9,997,386 |
Substrate holder mounting device and substrate holder container chamber A substrate holder mounting device is provided that is compact and has a simple structure. The substrate holder mounting device according to the present... |
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