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Patent # Description
US-9,996,364 Vehicle user interface adaptation
Methods, devices, and systems are used for a vehicle user interface adaption system. In an example, operations may be effectuated that include displaying a...
US-9,996,363 Methods of and apparatus for displaying windows on a display
In a compositing window system, as a respective version of the window for an application is written into a window buffer, a corresponding set of per tile...
US-9,996,362 Diagnostics only boot mode
Systems and methods for utilizing a diagnostics only boot mode may include initializing, by a computing device comprising a processor, a boot sequence. The...
US-9,996,361 Byte and nibble sort instructions that produce sorted destination register and destination index mapping
A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an...
US-9,996,360 Transaction abort instruction specifying a reason for abort
A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least...
US-9,996,359 Fast multi-width instruction issue in parallel slice processor
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an...
US-9,996,358 Unified prefetching into instruction cache and branch target buffer
A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes:...
US-9,996,357 Resolving page faults out of context for shared contexts
Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a...
US-9,996,356 Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor
Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example,...
US-9,996,355 Parsing-enhancement facility
An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the...
US-9,996,354 Instruction stream tracing of multi-threaded processors
A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last...
US-9,996,353 Universal history buffer to support multiple register types
An approach is provided in which a mapper control unit receives first dispatch information corresponding to a first instruction that identifies a first register...
US-9,996,352 ROM-code programmable digital signal processor
Systems, methods, and other embodiments associated with a processor that includes selectively enabled features are described. According to one embodiment, a...
US-9,996,351 Power management of branch predictors in a computer processor
A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such...
US-9,996,350 Hardware apparatuses and methods to prefetch a multidimensional block of elements from a multidimensional array
Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one...
US-9,996,349 Clearing specified blocks of main storage
Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is...
US-9,996,348 Zero cycle load
A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is...
US-9,996,347 Hardware apparatuses and methods relating to elemental register accesses
Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor...
US-9,996,346 Multifunctional hexadecimal instruction form system and program product
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT...
US-9,996,345 Variable length execution pipeline
In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock...
US-9,996,344 Customized runtime environment
Methods, systems, and computer program products for creating a customized runtime environment are described. One or more runtime environment capabilities are...
US-9,996,343 System and method for determining component version compatibility across a device ecosystem
A system and method that include collecting device version profiles from a plurality of device sources; classifying the device version profiles into a device...
US-9,996,342 Automatic detection of potential merge errors
In an approach to detection of potential merge errors when merging source code, a computer detects a source code merge process start. The computer compares at...
US-9,996,341 Infrastructure for the automation of the assembly of schema maintenance scripts
A method and apparatus to build a migration package. According to one embodiment of the invention, a plurality of programming elements are developed and stored...
US-9,996,340 Identifying user managed software modules
A computer program product for identifying user managed software modules includes program instructions for: receiving a request for a directed load of a...
US-9,996,339 Enhanced updating for digital content
Disclosed herein are systems, methods, and software to enhance updates to digital content. In at least one implementation, an update agent identifies from a set...
US-9,996,338 Synchronization of configuration changes between applications and their platforms
A method, system, and computer program product for handling synchronization of configuration changes between applications and their platforms. A computer...
US-9,996,337 Electronic apparatus, power supply device, system and apparatus
A power supply device is caused to execute a new program. An electronic apparatus that receives power from a power supply device in a non-contact manner...
US-9,996,335 Concurrent deployment in a network environment
Particular embodiments described herein provide for a communication system that can be configured to receive a request for an update to a plurality of devices...
US-9,996,334 Deploying and utilizing a software library and corresponding field programmable device binary
Examples of techniques for deploying a software library and a corresponding field programmable device binary are disclosed. In one example implementation...
US-9,996,333 Apparatus and method for automating the installation and configuration of infrastructure
Provided are an apparatus for automating the installation and configuration of infrastructure. The apparatus comprises, an installation information management...
US-9,996,332 Accurately estimating install time
Timing parameters that influence an install time interval for installing a product on computing machines in a test environment in accordance with an...
US-9,996,331 Customized application state transition
An example method for managing application deployment in a cloud environment may maintain a state machine. The state machine may include a plurality of...
US-9,996,330 Deployment process plugin architecture
A system, a method, and a computer program product for deploying objects are disclosed. A file containing a plurality of artifacts for deploying during runtime...
US-9,996,329 Translating atomic read-modify-write accesses
Various systems and methods for translating atomic read-modify-write accesses are described herein. In one example, a method includes determining that a machine...
US-9,996,328 Compiling and optimizing a computer code by minimizing a number of states in a finite machine corresponding to...
Methods and systems for compiling codes from programming languages into programming languages are disclosed. An example method may include acquiring a first...
US-9,996,327 Method, program, and system for code optimization
Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is...
US-9,996,326 Layered vector architecture compatibility for cross-system portability
An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on...
US-9,996,325 Dynamic reconfigurable compiler
In one example, a device includes one or more processors configured to determine a set of optimization pass configuration data for code of a software program to...
US-9,996,324 Cooperative creation of dataflow models using sparse random instrumentation
Dataflow analysis is provided by monitoring a first and a second computing device to detect an initiation of an application on one or more of these computing...
US-9,996,323 Methods and systems for utilizing bytecode in an on-demand service environment including providing multi-tenant...
Execution of code in a multitenant runtime environment. A request to execute code corresponding to a tenant identifier (ID) is received in a multitenant...
US-9,996,322 Dynamically generated user interface
A system and method for facilitating automatically adjusting a user interface display screen or portion thereof. An example method includes determining context...
US-9,996,321 Multi-tenant, tenant-specific applications
Customizations, made at various levels in the customization channel, are saved as separate sets of customization deltas that are applied to a base computing...
US-9,996,320 Fused multiply-add (FMA) low functional unit
An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP)...
US-9,996,319 Floating point (FP) add low instructions functional unit
An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low...
US-9,996,318 FIFO memory having a memory region modifiable during operation
A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state...
US-9,996,317 High speed and low power circuit structure for barrel shifter
A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives...
US-9,996,316 Mediation of wakeword response for multiple devices
Devices, systems, and methods provide synchronization of multiple voice-controlled devices to establish priority of one of the devices to respond to an acoustic...
US-9,996,315 Systems and methods using audio input with a mobile device
Systems and methods of using audio input with a mobile device. A method comprises receiving content at a mobile device; annotating, at the mobile device, a...
US-9,996,314 Audio control apparatus and headset system for integrating personal electronic devices
An audio control apparatus particularly suited for an active outdoor type of person integrates multiple electronic devices. Audio source devices can include a...
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