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Patent # Description
US-1,007,9257 Anti-reflective layer for backside illuminated CMOS image sensors
A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there...
US-1,007,9256 Image sensor pixels with light guides and light shield structures
A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures,...
US-1,007,9255 Color filter array apparatus
A color filter array apparatus is provided. The apparatus includes a first color filter array comprising color filters arranged in a first pattern and a second...
US-1,007,9254 Chip scale package and related methods
Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an...
US-1,007,9253 Imaging device and electronic device
An imaging device with excellent imaging performance is provided. The imaging device has a first circuit including a first photoelectric conversion element and...
US-1,007,9252 Display apparatus
A display apparatus includes an array substrate, a light emitting element, and a light shielding layer. The light emitting element is disposed on the array...
US-1,007,9251 Semiconductor device and manufacturing method thereof
An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor...
US-1,007,9250 Array substrate, its manufacturing method, and display device
The present disclosure provides an array substrate, its manufacturing method, and a display device. The method includes steps of forming a passivation layer on...
US-1,007,9249 Finfet devices with multiple channel lengths
A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle...
US-1,007,9248 Field-effect transistors with a buried body contact
Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a...
US-1,007,9247 Nonvolatile memory device and method of manufacturing the same
Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The...
US-1,007,9246 Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
US-1,007,9245 Semiconductor device and method for fabricating same
A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower...
US-1,007,9244 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-1,007,9243 Method of integrating a charge-trapping gate stack into a CMOS flow
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a...
US-1,007,9242 Logic and flash field-effect transistors
Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed...
US-1,007,9241 Method of manufacturing an EEPROM device
A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a first dielectric layer having a first thickness on the...
US-1,007,9240 Ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier...
US-1,007,9239 Compact three-dimensional mask-programmed read-only memory
A compact three-dimensional mask-programmed read-only memory (3D-MPROM.sub.C) is disclosed. Its memory array and a decoding stage thereof are formed on a same...
US-1,007,9238 Memory device and method for manufacturing the same
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as...
US-1,007,9237 Semiconductor memory device
A semiconductor memory device may include: a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area; a...
US-1,007,9236 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
US-1,007,9235 Memory cells and memory arrays
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to...
US-1,007,9234 Metal-insulator-metal capacitor analog memory unit cell
A memory device including a plurality of memory unit cells arranged in a crossbar configuration for a neural network is provided. Each of the memory unit cells...
US-1,007,9233 Semiconductor device and method of forming the semiconductor device
A method of forming a semiconductor device, includes forming first and second SiGe fins on a substrate, forming a protective layer on the first SiGe fin,...
US-1,007,9232 FinFET CMOS with silicon fin n-channel FET and silicon germanium fin p-channel FET
An advanced FinFET structure is described. A FinFET device includes a set of n-type FinFET devices and a set of p-type FinFET devices disposed on a substrate....
US-1,007,9231 Semiconductor device
A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third...
US-1,007,9230 Double-sided vertical semiconductor device with thinned substrate
A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped...
US-1,007,9229 Resistor fins
A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins...
US-1,007,9228 Tight integrated vertical transistor dual diode structure for electrostatic discharge circuit protector
An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated...
US-1,007,9227 Apparatus for rectified RC trigger of back-to-back MOS-SCR ESD protection
An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source...
US-1,007,9226 Semiconductor device
A semiconductor device comprises at least a semiconductor module including a semiconductor chip, a heat sink thermally connected to the semiconductor chip and a...
US-1,007,9225 Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP)...
Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP)...
US-1,007,9224 Interconnect structures for assembly of semiconductor structures including at least one integrated circuit...
A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a...
US-1,007,9223 Clips defining electrical pathway on a flexible sheet
A conductive pathway mounted on an electrically insulating sheet having an upper face and an opposed lower face, said sheet having a plurality of pairs of...
US-1,007,9222 Package-on-package structure and manufacturing method thereof
A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of...
US-1,007,9221 Semiconductor apparatus including a plurality of channels and through-vias
A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips may include a plurality of through-vias, each formed at...
US-1,007,9220 Package substrate having a plurality of chips electrically connected by conductive vias and wiring bonding
This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in...
US-1,007,9219 Power semiconductor contact structure and method for the production thereof
A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal molded body 2 as an electrode, which are...
US-1,007,9218 Test method for a redistribution layer
A conductive layer is formed on a first surface of a first carrier. The redistribution layer is formed on the conductive layer. Then an open-test is performed...
US-1,007,9217 Power semiconductor device load terminal
A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device...
US-1,007,9215 Electronic chip
An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity...
US-1,007,9214 Power semiconductor device
A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower...
US-1,007,9213 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device...
US-1,007,9212 Semiconductor device having solder groove
In order to restrict cracking or the like in a connection member such as solder, provided is a semiconductor device including a first component; a second...
US-1,007,9211 Modular interconnection repair of multi-die package
An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the...
US-1,007,9210 Integrated circuit device and method of fabricating the same
An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first...
US-1,007,9209 Graphene film manufacturing method and semiconductor device manufacturing method
A method of manufacturing a graphene film manufactures a graphene film in good state without generating wrinkles and stresses and leaving residues of the resin....
US-1,007,9208 IC structure with interface liner and methods of forming same
Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a...
US-1,007,9207 Metallization of the wafer edge for optimized electroplating performance on resistive substrates
A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an...
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