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Patent # Description
US-1,011,5833 Self-aligned heterojunction field effect transistor
A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate...
US-1,011,5832 Thin film transistor, method for manufacturing the same, array substrate and display device
A TFT is provided. The TFT includes an active layer, and the active layer includes a first active layer and a second active layer. The second active layer is...
US-1,011,5831 Semiconductor device having an oxide semiconductor layer comprising a nanocrystal
In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is...
US-1,011,5830 Semiconductor device, manufacturing method thereof, and electronic device
A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film. An interlayer insulating film is...
US-1,011,5828 Field-effect transistor, display element, image display device, and system
A field-effect transistor including: a gate electrode; a source electrode and a drain electrode; an active layer disposed to be adjacent to the source electrode...
US-1,011,5826 Semiconductor structure and the manufacturing method thereof
The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an...
US-1,011,5825 Structure and method for FinFET device with asymmetric contact
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin-type active region extruded from a...
US-1,011,5824 Forming a contact for a semiconductor device
A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion...
US-1,011,5823 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a...
US-1,011,5822 Methods of forming low band gap source and drain structures in microelectronic devices
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include...
US-1,011,5821 FDSOI LDMOS semiconductor device
Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For...
US-1,011,5820 Vertical transistors with sidewall gate air gaps and methods therefor
A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first...
US-1,011,5819 Recessed high voltage metal oxide semiconductor transistor for RRAM cell
A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a...
US-1,011,5818 Reducing MOSFET body current
An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, a first configuration switch, and a second configuration...
US-1,011,5817 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a...
US-1,011,5816 Semiconductor device and manufacturing method thereof
A semiconductor device is provided. The device includes an n- type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An...
US-1,011,5815 Transistor structures having a deep recessed P+ junction and methods for making same
A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the...
US-1,011,5814 Process method and structure for high voltage MOSFETs
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches...
US-1,011,5813 Semiconductor structure and method of forming the same
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the...
US-1,011,5812 Semiconductor device having a superjunction structure
A semiconductor device includes a drift region of a first conductivity type, an anode region of a second conductivity type situated below the drift region, an...
US-1,011,5811 Vertical channel semiconductor device with a reduced saturation voltage
A vertical channel semiconductor device including: a semiconductor body including a substrate having a first conductivity type and a front layer having a second...
US-1,011,5810 Heterojunction bipolar transistor with a thickened extrinsic base
Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is...
US-1,011,5809 Semiconductor memory device and method of manufacturing the same
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and...
US-1,011,5808 finFET device and methods of forming
A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending...
US-1,011,5807 Method, apparatus and system for improved performance using tall fins in finFET devices
At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A...
US-1,011,5805 Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation
A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer...
US-1,011,5804 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer...
US-1,011,5803 Field-effect transistor and method for the fabrication thereof
The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound...
US-1,011,5802 Manufacturing method for compound semiconductor device
A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth...
US-1,011,5801 Vertical transistor gated diode
After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped...
US-1,011,5800 Vertical fin bipolar junction transistor with high germanium content silicon germanium base
A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a...
US-1,011,5799 Non-volatile memory devices and manufacturing methods thereof
There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of...
US-1,011,5798 Semiconductor device and method of manufacturing the same
A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be...
US-1,011,5797 Finfet semiconductor device and method of manufacturing the same
In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor...
US-1,011,5796 Method of pulling-back sidewall metal layer
A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate,...
US-1,011,5795 Semiconductor device and method of manufacturing same
To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate...
US-1,011,5794 Semiconductor device comprising accumulation layer channel and inversion layer channel
A semiconductor device includes: an n- type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n- type...
US-1,011,5793 Semiconductor device
An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality...
US-1,011,5792 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode,...
US-1,011,5791 Semiconductor device including a super junction structure in a SiC semiconductor body
An embodiment of a semiconductor device includes a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type. A super...
US-1,011,5790 Electronic device including an insulating structure
An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the...
US-1,011,5789 Nonvolatile memory cell with improved isolation structures
A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor...
US-1,011,5788 Semiconductor devices with horizontal gate all around structure and methods of forming the same
A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed...
US-1,011,5787 Low leakage FET
FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function...
US-1,011,5786 Capacitor and method for fabricating the same
A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between...
US-1,011,5785 Memory cells and devices
Disclosed are memory cells that include a mixture of an acrylic polyol, an alkylene urea-glyoxal resin, and an acid catalyst, and memory devices that contain a...
US-1,011,5784 Semiconductor device, MIM capacitor and associated fabricating method
The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate; a first dielectric layer over the...
US-1,011,5783 Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the...
A semiconductor device includes a semiconductor substrate including a semiconductor chip formation region, a chip internal circuit provided within the...
US-1,011,5782 Display device with durable wiring
Provided is a display device which has a rectangular display region with four sides. The display region includes a gate line, a signal line, a first sub-pixel...
US-1,011,5781 Organic light-emitting diode display
A pixel array substrate includes a first substrate, pixel units, data lines, scan lines, constant voltage lines, a constant voltage source, a constant voltage...
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